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參數(shù)資料
| 型號(hào)： | AM79C978AVCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 5 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 174/256頁(yè) |
| 文件大小： | 3505K |
| 代理商： | AM79C978AVCW |
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174
Am79C978A
6-0
PMR_ADDR
Pattern Match Ram Address.
These bits are the Pattern Match
Ram address to be written to or
read from.
These bits are read and write ac-
cessible always. PMR_ADDR is
reset to 0 after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
BCR46: OnNow Pattern Matching Register 2
Note:
This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
PMR_B2
Pattern Match RAM Byte 2. This
byte is written into or read from
Byte 2 of the Pattern Match RAM.
These bits are read and write ac-
cessible always. PMR_B2 is un-
defined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
7-0
PMR_B1
Pattern Match RAM Byte 1. This
byte is written into or read from
Byte 1 of Pattern Match RAM.
These bits are read and write ac-
cessible always. PMR_B1 is un-
defined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
BCR47: OnNow Pattern Matching Register 3
Note:
This register is used to control and indirectly ac-
cess the Pattern Match RAM (PMR). When BCR45 is
written and the PMAT_MODE bit (bit 7) is 1, Pattern
Match logic is enabled. No bus accesses into PMR are
possible, and BCR46, BCR47, and all other bits in
BCR45 are ignored. When PMAT_MODE is set, a read
of BCR45, BCR46, or BCR47 returns all undefined bits
except for PMAT_MODE.
When BCR45 is written and the PMAT_MODE bit is 0,
the Pattern Match logic is disabled and accesses to the
PMR are possible. Bits 6-0 of BCR45 specify the ad-
dress of the PMR word to be accessed. Following the
write to BCR45, the PMR word may be read by reading
BCR45, BCR46 and BCR47 in any order. To write to
PMR word, the write to BCR45 must be followed by a
write to BCR46 and a write to BCR47 in that order to
complete the operation. The RAM will not actually be
written until the write to BCR47 is complete. The write
to BCR47 causes all 5 bytes (four bytes of BCR46-47
and the upper byte of the BCR45) to be written to what-
ever PMR word is addressed by bits 6:0 of BCR45.
When PMAT_MODE is 0, the contents of the word ad-
dressed by bits 6:0 of BCR45 can be read by reading
BCR45-47 in any order.
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8
PMR_B4
Pattern Match RAM Byte 4. This
byte is written into or read from
Byte 4 of Pattern Match RAM.
These bits are read and write ac-
cessible always. PMR_B4 is un-
defined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
7-0
PMR_B3
Pattern Match RAM Byte 3. This
byte is written into or read from
Byte 3 of Pattern Match RAM.
These bits are read and write ac-
cessible always. PMR_B3 is un-
defined after H_RESET, and is
unaffected by S_RESET and the
STOP bit.
BCR48: LED4 Status
This register defines the functionality of LED4. LED4
will default to indicating the selected SPEED with Pulse
stretching enabled (default = 0082h).
BCR48 controls the function(s) that the LED4 pin dis-
plays. Multiple functions can be simultaneously en-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978KC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978VC/W | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C979BKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C98 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Twisted-Pair Ethernet Transceiver (TPEX) |
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