32
Am79C978A
The Auto-Poll
’
s frequency of generating MII man-
agement frames can be adjusted by setting of the
APDW bits (BCR32, bits 10-8). The delay can be
adjusted from 0 MDC periods to 2048 MDC periods.
Auto-Poll by default will only read the MII Status
register in the external PHY.
Network Port Manager
If the external PHY is present and is active, the Net-
work Port Manager will request status from the external
PHY by generating MII management frames. These
frames will be sent roughly every 900 ms. These
frames are necessary so that the Network Port Man-
ager can monitor the current active link and can select
a different network port if the current link goes down.
10BASE-T PHY
The 10BASE-T transceiver incorporates the physical layer
function, including both clock recovery (ENDEC) and trans-
ceiver function. Data transmission over the 10BASE-T me-
dium requires an integrated 10BASE-T MAU. The
transceiver will meet the electrical requirements for
10BASE-T as specified in IEEE 802.3i. The transmit signal
is filtered on the transceiver to reduce harmonic content per
IEEE 802.3i. Since filtering is performed in silicon, external
filtering modules are not needed. The 10BASE-T PHY
transceiver receives 10 Mbps data from the MAC across
the internal MII at 2.5 million nibbles per second (parallel),
or 10 million bits per second (serial) for 10BASE-T. It then
Manchester encodes the data before transmission to the
network.
The RX+ pins are differential twisted-pair receivers.
When properly terminated, each receiver will meet
the electrical requirements for 10BASE-T as speci-
fied in IEEE 802.3i. Each receiver has internal filter-
ing and does not require external filter modules. The
10BASE-T PHY transceiver receives a Manchester
coded 10BASE-T data stream from the medium. It
then recovers the clock and decodes the data. The
data stream is presented at the internal MII interface
in either parallel or serial format.
PCI and JTAG Configuration Information
The PCI device ID and software configuration information
is as follows in Table 4 and Table 5.
Table 4.
PCI Device ID
Table 5.
PCI Software Configuration
Slave Bus Interface Unit
The slave Bus Interface Unit (BIU) controls all ac-
cesses to the PCI configuration space, the Control
and Status Registers (CSR), the Bus Configuration
Registers (BCR), the Address PROM (APROM) loca-
tions, and the Expansion ROM. Table 6 shows the re-
sponse of the Am79C978A controller to each of the
PCI commands in slave mode.
Table 6.
Slave Commands
Slave Configuration Transfers
The host can access the PCI configuration space with
a configuration read or write command. The
Am79C978A controller will assert DEVSEL during the
address phase when IDSEL is asserted, AD[1:0] are
both 0, and the access is a configuration cycle. AD[7:2]
select the DWord location in the configuration space.
The Am79C978A controller ignores AD[10:8], because
Vendor ID
Device ID
Rev ID (offset 0x08)
1022
2001
52
CSR89
CSR88
JTAG
00002262
00006003h
2262 6003h
C[3:0]
Command
Use
0000
Interrupt
Acknowledge
Not used
0001
Special Cycle
Not used
0010
I/O Read
Read of CSR, BCR, APROM,
and Reset registers
0011
I/O Write
Write to CSR, BCR, and
APROM
0100
Reserved
0101
Reserved
0110
Memory Read
Memory mapped I/O read of
CSR, BCR, APROM, and
Reset registers. Read of the
Expansion Bus
0111
Memory Write
Memory mapped I/O write of
CSR, BCR, and APROM
1000
Reserved
1001
Reserved
1010
Configuration
Read
Read of the Configuration
Space
1011
Configuration
Write
Write to the Configuration
Space
1100
Memory Read
Multiple
Aliased to Memory Read
1101
Dual Address
Cycle
Not used
1110
Memory Read
Line
Aliased to Memory Read
1111
Memory Write
Invalidate
Aliased to Memory Write