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參數(shù)資料
| 型號： | AN-937 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Gate Drive Characteristics and Requirements for HEXFET |
| 中文描述： | 門驅(qū)動器的特點及要求的HEXFET |
| 文件頁數(shù)： | 11/21頁 |
| 文件大?。?/td> | 418K |
| 代理商： | AN-937 |
AN-937 (v.Int)
They have the additional advantage of providing a negative gate bias. One additional limitation of pulse transformers is the fact
that the gate drive impedance is seriously degraded by the leakage inductance of the transformer. Best results are normally
obtained with a few turns of twisted AWG30 wire-wrap wire on a small ferrite core.
Lower gate drive impedance and a wider duty-cycle range can be obtained with the circuit in Figure 24a. In this circuit, Q1 and
Q2 (a single Micro-8 package) are used to buffer the input and drive the primary of the transformer. The complementary MOS
output stage insures low output impedance and performs wave shaping. The output stage is fed by a dc restorer made by C2 and
D1 that references the signal to the positive rail. D1 and D2 are also used to generate the gate drive voltage.
The input and output wave form with 1nF load capacitance are shown in Figure 24b. The turn-on and turn-off delays are 50ns.
The rise and fall times are determined by the 10 Ohm resistor and the capacitive load. This circuit will operate reliably between
20 and 500 kHz, with on/off times from 0.5 to 15 microsecs.
Due to the lack of an under voltage lock-out feature, the power-up and power down behavior of the circuit is important.
Intentionally C1 and C2 are much bigger in value then C3 so that the voltage across C3 rises to an adequate level during the first
incoming pulse. The power-up wave forms at 50kHz switching frequency and 50% duty cycle are shown in Figure 25. During
the first pulse, the output voltage is 10V only, and drops back below 10V at the fifth pulse.
Gate voltage: 10V/div.
Drain voltage: 200V/div.
C2 ripple voltage: 1V/div
Horiz: 2
μ
s/div
Figure 20.
Waveforms of the circuit in
Figure 23a. with C1=680pF, R3=1k,
f=100kHz.
File: gps-4.plt
10
20
30
40
Frequency (kHz)
50
60
70
80
100
Z
Figure 21
. Zener current (max output current)
for the circuit in Figure 23a.
with C1 = 680pF, R3 = 1k
20
10
0
90
C2 voltage: 5V/div
Horiz: 100
μ
s/div.
Figure 22.
Start-up voltage at 100 kHz for the
circuit in Figure 23a. with C1=680pF, R3=R3=1k
File: GPS-6.plt
0
V
GS
Figure 23.
Volt-seconds across
winding must balance
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