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參數(shù)資料
| 型號： | AN-937 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Gate Drive Characteristics and Requirements for HEXFET |
| 中文描述： | 門驅動器的特點及要求的HEXFET |
| 文件頁數(shù)： | 17/21頁 |
| 文件大小： | 418K |
| 代理商： | AN-937 |
AN-937 (v.Int)
Common source inductance plays a significant role in switching performance. In the circuit of Figure 31a the switching
performance is degraded due to the fact that V
GS
is reduced by (L
S
+ L
W
) di/dt, where di/dt is the rate of change of the drain
current. By eliminating L
W
from the drive circuit, V
GS
can approach the applied drive voltage because only L
S
(the internal
source inductance) is common.
This can be done by separately connecting the power return and the drive signal return to the source pin of the switching
HEXFET
, as shown in Figure 31b. Thus, the load current I
D
does not flow through any of the external wiring of the drive
circuit; consequently, only the internal source inductance L
S
is common to both load and drive circuits.
In the case of logic level HEXFET
s, for which V
GS
is 5V and not 10V, the loss of drive voltage due to common mode
inductance has proportionately twice the effect as it would on a 10V drive signal, even though actual values of L
S
and L
W
are the
same.
8.3 Resistive Switching Tests
In the following tests of switching performance, the physical layout of the test circuit was carefully executed so to minimize the
common source inductance. The following precautions were also observed:
1. R
L
was built by paralleling 0.5W resistors to achieve the desired load resistance (see Table 5).
2. To minimize inductance in the load circuit, a 10
μ
F low-ESR low-ESL capacitor was connected directly from +V
DD
to the
source of the DUT.
3. To provide a low source impedance for the 5V gate pulse of the DUT, a 0.1
μ
F low-ESR low-ESL capacitor was connected
directly between pin 14 and pin 7 of the driver IC.
4. To provide minimum common source impedance, the source of the DUT was the common return point of all ac and dc
system grounds.
5. To reduce stray inductances and thus achieve maximum switching speeds, the physical size of the high current loop (R
L
,
DUT, 10
μ
F) was reduced to the smallest practical limits.
Only the 5 volt families have been tested as logic level HEXFET
drives: bipolar and CMOS (and their derivatives), as indicated
below.
TTL GATES
DM7400N:
74F00PC:
DM74S00N:
DM74LS00N:
DM74AS00N:
Standard TTL
High Speed TTL
Schottky TTL
Low Power Schottky TTL
Advanced Schottky TTL
+V
DD
= 0.5 BV
DSS
Figure 32.
Switching test circuit. Logic level driver is one-quarter of a quad
NAND gate.
R
L
DUT
+5V
0.1pF
0.1pF
3
15
1
2
7, 4, 5, 9
10, 12, 13
50
V
SS
+5V
0
SIG. GEN.
SCOPE
To Order
Index
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