參數(shù)資料
型號: AN-937
廠商: Electronic Theatre Controls, Inc.
英文描述: Gate Drive Characteristics and Requirements for HEXFET
中文描述: 門驅(qū)動器的特點及要求的HEXFET
文件頁數(shù): 7/21頁
文件大?。?/td> 418K
代理商: AN-937
AN-937 (v.Int)
Standard Buffered
Outputs
4049 / 4050 Drivers
Logic Supply Voltage
Logic Conditions
Logic Zero:
Approximate sink current
for V
OL
< 1.5V
Logic One:
Minimum source current for V
OH
Typical switching times of logic drive signals:
RISE
FALL
5V
10V
15V
5V
10V
15V
1.5mA
3.5mA
4mA
20mA
40mA
40mA
-0.5mA
> 4.6V
-13mA
> 9.5V
-3.4mA
> 13.5V
-1.25mA
> 2.5V
-1.25mA
> 9.5V
-3.75mA
> 13.5V
100ns
100ns
50ns
50ns
40ns
40ns
100ns
40ns
50ns
20ns
40ns
15ns
Table 2.
Driving HEXFET
s from C-MOS (Buffered)
When analog signals determine the switching frequency or
duty cycle of a HEXFET
, as in PWM applications, a
voltage comparator is normally used to command the
switching. Here, too, the limiting factors are the slew rate of
the comparator and its current drive capability. Response
times under 40ns can be obtained at the price of low output
voltage swing (TTL compatible). Once again, the use of
output buffers like the ones shown in Figures 9, may be
necessary to improve drive capability and dv/dt immunity. If
better switching speeds are desired. a fast op-amp should be
used.
In many applications, when the HEXFET
is turned on,
current transfers from a freewheeling diode into the
HEXFET
. If the switching speed is high and the stray
inductances in the diode path are small, this transfer can
occur in such a short time as to cause a reverse recovery
current in the diode high enough to short out the dc bus. For
this reason, it may be necessary to slow down the turn-on of
the HEXFET
while leaving the turn-off as fast as practical.
Low impedance pulse shaping circuits can be used for this
purpose, like the ones in Figures 12 and 13.
7. DRIVE CIRCUITS NOT
REFERENCED TO GROUND
To drive a HEXFET
into saturation, an appropriate voltage
must be applied between the gate and source. If the load is
connected between source and ground, and the drive voltage is
applied between gate and ground, the effective voltage between
gate and source decreases as the device turns on. An equilibrium
point is reached in which the amount of current flowing in the
load is such that the voltage between gate and source maintains
that amount of drain current and no more. Under these
conditions the voltage drop across the MOSFET is certainly
higher than the threshold voltage and the power dissipation can
be very high. For this reason, the gate drive circuit is normally
referenced to the source rather than to the ground. There are
Figure 10.
Dual Supply Op-Amp Drive Circuit
V
H
LOAD
+12V
INPUTS
8
7
2
4
5
6
1
3
IRF7309 OR IRF7509
-
+
-12V
0.1
μ
F
CER
FET
INPUT
OP
AMP
Figure 11.
Single Supply Op-Amp Drive Circuit
(Voltage Follower)
CA3103
+
V
H
LOAD
+12V
8
7
2
4
5
6
1
3
IRF7307 OR IRF7507
-
0.1
μ
F
CER
FET
INPUT
OP AMP.
2
3
To Order
Index
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