參數(shù)資料
型號： C8051F010-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 123/171頁
文件大?。?/td> 0K
描述： BOARD PROTOTYPING W/C8051F010
標(biāo)準(zhǔn)包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
8.
COMPARATORS
The MCU family has two on-chip analog voltage comparators as shown in Figure 8.1.
The inputs of each
Comparator are available at the package pins. The output of each comparator is optionally available at the package
pins via the I/O crossbar (see Section 15.1). When assigned to package pins, each comparator output can be
programmed to operate in open drain or push-pull modes (see section 15.3).
The hysteresis of each comparator is software-programmable via its respective Comparator control register
(CPT0CN, CPT1CN).
The user can program both the amount of hysteresis voltage (referred to the input voltage)
and the positive and negative-going symmetry of this hysteresis around the threshold voltage. The output of the
comparator can be polled in software, or can be used as an interrupt source. Each comparator can be individually
enabled or disabled (shutdown). When disabled, the comparator output (if assigned to a Port I/O pin via the
Crossbar) defaults to the logic low state, its interrupt capability is suspended and its supply current falls to less than
1
A. Comparator 0 inputs can be externally driven from -0.25V to (AV+) + 0.25V without damage or upset.
The Comparator 0 hysteresis is programmed using bits 3-0 in the Comparator 0 Control Register CPT0CN (shown
in Figure 8.3). The amount of negative hysteresis voltage is determined by the settings of the CP0HYN bits. As
shown in Figure 8.2, settings of 10, 4 or 2mV of negative hysteresis can be programmed, or negative hysteresis can
be disabled. In a similar way, the amount of positive hysteresis is determined by the setting the CP0HYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Interrupt
enable and priority control, see Section 10.4). The CP0FIF flag is set upon a Comparator 0 falling-edge interrupt,
and the CP0RIF flag is set upon the Comparator 0 rising-edge interrupt. Once set, these bits remain set until cleared
by the CPU. The Output State of Comparator 0 can be obtained at any time by reading the CP0OUT bit. Note the
comparator output and interrupt should be ignored until the comparator settles after power-up. Comparator 0 is
enabled by setting the CP0EN bit, and is disabled by clearing this bit. Note there is a 20usec settling time for the
comparator output to stabilize after setting the CP0EN bit or a power-up. Comparator 0 can also be programmed as
a reset source. For details, see Section 13.
The operation of Comparator 1 is identical to that of Comparator 0, except the Comparator 1 is controlled by the
CPT1CN Register (Figure 8.4). Comparator 1 can not be programmed as a reset source. Also, the input pins for
Comparator 1 are not pinned out on the F002, F007, F012, or F017 devices. The complete electrical specifications
for the Comparators are given in Table 8.1.
Figure 8.1. Comparator Functional Block Diagram
+
-
AV+
Q
SET
CLR
D
Q
SET
CLR
D
Crossbar
Interrupt
Handler
Reset
Decision
Tree
(SYNCHRONIZER)
CP0+
CP0-
AGND
CP
T0CN
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
+
-
AV+
Q
SET
CLR
D
Q
SET
CLR
D
Crossbar
Interrupt
Handler
(SYNCHRONIZER)
CP1+
CP1-
AGND
CP
T1CN
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
not available on F002,
F007, F012, and F017
55
Rev. 1.7
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