參數(shù)資料
型號: C8051F010-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 32/171頁
文件大小: 0K
描述: BOARD PROTOTYPING W/C8051F010
標準包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
17.4.
SPI Special Function Registers
The SPI is accessed and controlled through four special function registers in the system controller: SPI0CN Control
Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four
special function registers related to the operation of the SPI Bus are described in the following section.
Figure 17.5. SPI0CFG: SPI Configuration Register
R/W
R
R/W
Reset Value
CKPHA
CKPOL
BC2
BC1
BC0
SPIFRS2
SPIFRS1
SPIFRS0
00000111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x9A
Bit7:
CKPHA: SPI Clock Phase.
This bit controls the SPI clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
Bit6:
CKPOL: SPI Clock Polarity.
This bit controls the SPI clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Bits5-3: BC2-BC0: SPI Bit Count.
Indicates which of the up to 8 bits of the SPI word have been transmitted.
BC2-BC0
Bit Transmitted
0
Bit 0 (LSB)
0
1
Bit 1
0
1
0
Bit 2
0
1
Bit 3
1
0
Bit 4
1
0
1
Bit 5
1
0
Bit 6
1
Bit 7 (MSB)
Bits2-0: SPIFRS2-SPIFRS0: SPI Frame Size.
These three bits determine the number of bits to shift in/out of the SPI shift register
during a data transfer in master mode. They are ignored in slave mode.
SPIFRS
Bits Shifted
0
1
0
1
2
0
1
0
3
0
1
4
1
0
5
1
0
1
6
1
0
7
1
8
.
127
Rev. 1.7
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