參數(shù)資料
型號(hào)： C8051F010-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 43/171頁
文件大?。?/td> 0K
描述： BOARD PROTOTYPING W/C8051F010
標(biāo)準(zhǔn)包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 18.9. SCON: Serial Port Control Register
R/W
Reset Value
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0x98
Bits7-6: SM0-SM1: Serial Port Operation Mode.
These bits select the Serial Port Operation Mode.
SM0
SM1
Mode
0
Mode 0: Synchronous Mode
0
1
Mode 1: 8-Bit UART, Variable Baud Rate
1
0
Mode 2: 9-Bit UART, Fixed Baud Rate
1
Mode 3: 9-Bit UART, Variable Baud Rate
Bit5:
SM2: Multiprocessor Communication Enable.
The function of this bit is dependent on the Serial Port Operation Mode.
Mode 0: No effect
Mode 1: Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI will only be activated if stop bit is logic level 1.
Mode 2 and 3: Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI is set and an interrupt is generated only when the ninth bit is logic 1.
Bit4:
REN: Receive Enable.
This bit enables/disables the UART receiver.
0: UART reception disabled.
1: UART reception enabled.
Bit3:
TB8: Ninth Transmission Bit.
The logic level of this bit will be assigned to the ninth transmission bit in Modes 2 and 3. It
is not used in Modes 0 and 1. Set or cleared by software as required.
Bit2:
RB8: Ninth Receive Bit.
The bit is assigned the logic level of the ninth bit received in Modes 2 and 3. In Mode 1, if
SM2 is logic 0, RB8 is assigned the logic level of the received stop bit. RB8 is not used in
Mode 0.
Bit1:
TI: Transmit Interrupt Flag.
Set by hardware when a byte of data has been transmitted by the UART (after the 8
th bit in
Mode 0, or at the beginning of the stop bit in other modes). When the UART interrupt is
enabled, setting this bit causes the CPU to vector to the UART interrupt service routine.
This bit must be cleared manually by software
Bit0:
RI: Receive Interrupt Flag.
Set by hardware when a byte of data has been received by the UART (after the 8
th bit in
Mode 0, or after the stop bit in other modes – see SM2 bit for exception). When the
UART interrupt is enabled, setting this bit causes the CPU to vector to the UART interrupt
service routine. This bit must be cleared manually by software.
137
Rev. 1.7
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