參數(shù)資料
型號: C8051F010-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 83/171頁
文件大小: 0K
描述: BOARD PROTOTYPING W/C8051F010
標(biāo)準(zhǔn)包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.8.
Comparators and DACs
The C8051F000 MCU Family has two 12-bit DACs and two comparators on chip (the second comparator, CP1, is
not bonded out on the F002, F007, F012, and F017). The MCU data and control interface to each comparator and
DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown
mode.
The comparators have software programmable hysteresis. Each comparator can generate an interrupt on its rising
edge, falling edge, or both. The comparators’ output state can also be polled in software. These interrupts are
capable of waking up the MCU from idle mode. The comparator outputs can be programmed to appear on the Port
I/O pins via the Crossbar.
The DACs are voltage output mode and use the same voltage reference as the ADC. They are especially useful as
references for the comparators or offsets for the differential inputs of the ADC.
Figure 1.11. Comparator and DAC Diagram
SFR's
(Data
and
Cntrl)
CP1
CP1+
CP1-
DAC0
DAC1
REF
CP0
CP0+
CP0-
CIP-51
and
Interrupt
Handler
CROSSBAR
CP1
CP0
(Port I/O)
+
-
CP0
+
-
CP1
(not bonded out on
F002, F007, F012, and
F017)
19
Rev. 1.7
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