參數(shù)資料
型號： C8051F010-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 156/171頁
文件大小： 0K
描述： BOARD PROTOTYPING W/C8051F010
標(biāo)準(zhǔn)包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.5.
Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the
CPU while leaving the external peripherals and internal clocks active.
In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since
clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle.
Stop mode consumes the least power.
describes the Power Control Register (PCON) used to control the CIP-51’s power management modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power management
of the entire MCU is better accomplished by enabling/disabling individual peripherals as needed. Each analog
peripheral can be disabled when not in use and put into low power mode. Digital peripherals, such as timers or
serial buses, draw little power whenever they are not in use. Turning off the oscillator saves even more power, but
requires a reset to restart the MCU.
10.5.1. Idle Mode
Setting the Idle Mode Select bit (PCON.0) causes the CIP-51 to halt the CPU and enter Idle mode as soon as the
instruction that sets the bit completes.
All internal registers and memory maintain their original data. All analog
and digital peripherals can remain active during Idle mode.
Idle mode is terminated when an enabled interrupt or /RST is asserted. The assertion of an enabled interrupt will
cause the Idle Mode Selection bit (PCON.0) to be cleared and the CPU will resume operation. The pending
interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will be the
instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated by an internal
or external reset, the CIP-51 performs a normal reset sequence and begins program execution at address 0x0000.
Note: If the instruction following the write of the IDLE bit is a single-byte instruction and an interrupt occurs during
the execution phase of the instruction that sets the IDLE bit, the CPU may not wake from Idle mode when a future
interrupt occurs. Any instructions that set the IDLE bit should be followed by an instruction that has 2 or more op-
code bytes, for example:
// in ‘C’:
PCON |= 0x01;
// set IDLE bit
PCON = PCON;
// ... followed by a 3-cycle dummy instruction
; in assembly:
ORL PCON, #01h
; set IDLE bit
MOV PCON, PCON
; ... followed by a 3-cycle dummy instruction
If enabled, the WDT will eventually cause an internal watchdog reset and thereby terminate the Idle mode. This
feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the
PCON register. If this behavior is not desired, the WDT may be disabled by software prior to entering the Idle
mode if the WDT was initially configured to allow this operation. This provides the opportunity for additional
power savings, allowing the system to remain in the Idle mode indefinitely, waiting for an external stimulus to wake
up the system. Refer to Section 13.8 Watchdog Timer for more information on the use and configuration of the
WDT.
10.5.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruction that sets
the bit completes.
In Stop mode, the CPU and oscillators are stopped, effectively shutting down all digital
peripherals. Each analog peripheral must be shut down individually prior to entering Stop Mode. Stop mode can
only be terminated by an internal or external reset. On reset, the CIP-51 performs the normal reset sequence and
begins program execution at address 0x0000.
85
Rev. 1.7
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