參數(shù)資料
型號: CAT28F512
英文描述: 512K-Bit CMOS Flash Memory(512K(64K x 8位)位CMOS閃速存儲器)
中文描述: 為512k位CMOS閃存(為512k(64K的× 8位)位的CMOS閃速存儲器)
文件頁數(shù): 13/14頁
文件大?。?/td> 97K
代理商: CAT28F512
CAT28F512
13
Preliminary
Doc. No. 25042-00 2/98 F-1
ADDRESSES
WE (E)
OE (G)
CE (W)
DATA (I/O)
VCC
VPP
tWC
tWC
tRC
tAVEL
tELAX
tWLEL
tWLEL
tEHQZ
tDF
tGHEL
tEHEL
tEHEH
tEHGL
tELEH
HIGH-Z
DATA IN
= 40H
DATA IN
DATA IN
= C0H
VALID
DATA OUT
tEHDX
tOLZ
tOE
tOH
tLZ
tCE
tVPEL
VPPH
VPPL
0V
5.0V
VCC POWER-UP
& STANDBY
SETUP PROGRAM
COMMAND
LATCH ADDRESS
& DATA
PROGRAMMING
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
VCC STANDBY
tWLEL
tEHWH
tEHWH
tEHWH
tELEH
tDVEH
tDVEH
tDVEH
tEHDX
tEHDX
Abort/Reset
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
Figure 8. Alternate A.C. Timing for Program Operation
28F512 F10
POWER UP/DOWN PROTECTION
The CAT28F512 offers protection against inadvertent
programming during V
PP
and V
CC
power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, V
PP
and V
CC
may power up in any order. Additionally V
PP
may be
hardwired to V
PPH
independent of the state of V
CC
and
any power up/down cycling. The internal command
register of the CAT28F512 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1
μ
F ceramic
capacitor between V
CC
and V
SS
and V
PP
and V
SS
. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
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