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參數(shù)資料
| 型號： | CDB4392 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 2/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS4392 |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -10°C ~ 70°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4392 |
| 相關(guān)產(chǎn)品： | 598-1065-5-ND - IC DAC 24BIT 192KHZ W/VC 20TSSOP |
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CS4392
10
DS459PP3
3.4
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4392 incorpo-
rates selectable interpolation filters for each mode of operation. A fast and a slow roll-off filter is available
in each of Single, Double, and Quad Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. Bit 5 of the Mode Control 3 register (06h) is used to select which filter
is used. Filter specifications can be found in Section 8, and filter response plots can be found in Figures 12
to 35.
In stand-alone mode, only the fast roll-off filter is available.
3.5
System Clocking
The required MCLK to LRCK and suggested SCLK to LRCK ratios are outlined in table 1. MCLK can be
at any phase in regards to LRCK and SCLK. SCLK, LRCK and SDATA must meet the phase and timing
relationships outlined in Section 7. Some common MCLK frequencies have been outlined in tables 2 to 4.
*Note:These clocking ratios are only available in Control Port Mode when the MCLK Divide bit is enabled.
MCLK/LRCK
SCLK/LRCK
LRCK
Single Speed
256, 384, 512, 768, 1024*
32, 48, 64, 96, 128
Fs
Double Speed
128, 192, 256, 384, 512*
32, 48, 64
Fs
Quad Speed
64
32 (16 bits only)
Fs
96
32, 48
Fs
128, 256*
32, 64
Fs
192
32, 48, 64, 96
Fs
Table 1. Clock Ratios
Sample Rate
(kHz)
MCLK (MHz)
See Note
256x
384x
512x
768x
1024x*
32
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
Table 2. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
See Note
128x
192x
256x
384x
512x*
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
Table 3. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
See Note
64x
96x
128x
192x
256x*
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Table 4. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
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