SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND, logic 1 = VL) " />
參數(shù)資料
型號(hào): CDB4392
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 29/40頁(yè)
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS4392
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 2
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -10°C ~ 70°C
已供物品:
已用 IC / 零件: CS4392
相關(guān)產(chǎn)品: 598-1065-5-ND - IC DAC 24BIT 192KHZ W/VC 20TSSOP
CS4392
DS459PP3
35
SWITCHING CHARACTERISTICS - SPI CONTROL PORT (Inputs: logic 0 = AGND,
logic 1 = VL)
Notes: 7. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
8. Data must be held for sufficient time to bridge the transition time of CCLK.
9. For FSCK < 1 MHz
Parameter
Symbol
Min
Max
Unit
SPI Mode
CCLK Clock Frequency
fsclk
-6
MHz
RST Rising Edge to CS Falling
tsrs
500
-
ns
CCLK Edge to CS Falling
(Note 7)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
s
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
82
-
ns
CCLK High Time
tsch
82
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time
(Note 8)
tdh
15
-
ns
Rise Time of CCLK and CDIN
(Note 9)
tr2
-100
ns
Fall Time of CCLK and CDIN
(Note 9)
tf2
-100
ns
t r2
t f2
t dsu t dh
t sch
t scl
CS
CCL K
CD IN
t css
t csh
t spi
t srs
RST
Figure 39. SPI Control Port Timing
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