參數(shù)資料
型號(hào): CDB8420
廠商: Cirrus Logic Inc
文件頁數(shù): 26/94頁
文件大小: 0K
描述: EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻,采樣率轉(zhuǎn)換器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS8420
主要屬性: 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性: 44.1、48、96 kHz 輸出采樣率,AES/EBU,S/PDIF,EIAJ-340,GUI
已供物品:
相關(guān)產(chǎn)品: 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱: 598-1782
32
DS245F4
CS8420
10. CONTROL PORT REGISTER BIT DEFINITIONS
10.1
Memory Address Pointer (MAP)
This register defaults to 01
INCR
Auto-Increment Address Control Bit
0 -
Auto-increment address off
1 -
Auto-increment address on
MAP6-MAP0
Register address and function list
0 -
Reserved
1 -
Misc. Control 1
2 -
Misc. Control 2
3 -
Data Flow Control
4 -
Clock Source Control
5 -
Serial Audio Input Port Data Format
6 -
Serial Audio Output Port Data Format
7 -
Interrupt Register 1 Status
8 -
Interrupt Register 2 Status
9 -
Interrupt Register 1 Mask
10 -
Interrupt Register1 Mode (MSB)
11 -
Interrupt Register 1 Mode (LSB)
12 -
Interrupt Register 2 Mask
13 -
Interrupt Register 2 Mode (MSB)
14 -
Interrupt Register 2 Mode (LSB)
15 -
Receiver Channel Status Bits
16 -
Receiver Error Status
17 -
Receiver Error Mask
18 -
Channel Status Data Buffer Control
19 -
User Data Buffer Control
20 to 29 -
Q-channel Subcode Bytes 0 to 9
30 -
Sample Rate Ratio
31 -
Reserved
32 to 55 -
C-bit or U-bit Data Buffer
56 to 126 - Reserved
127 -
Chip ID and version register
Reserved registers must not be written to during normal operation. Some reserved registers are used for
test modes, which can completely alter the normal operation of the CS8420.
7
6
5
4
32
10
INCR
MAP6
MAP5
MAP4
MAP3
MAP2
MAP1
MAP0
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