參數(shù)資料
型號: CDB8420
廠商: Cirrus Logic Inc
文件頁數(shù): 37/94頁
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS8420
標準包裝: 1
主要目的: 音頻,采樣率轉換器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS8420
主要屬性: 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉換器
次要屬性: 44.1、48、96 kHz 輸出采樣率,AES/EBU,S/PDIF,EIAJ-340,GUI
已供物品:
相關產(chǎn)品: 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱: 598-1782
42
DS245F4
CS8420
10.12 Interrupt 2 Register Mask (0Ch)
The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error is
considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask
bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the
status register. The bit positions align with the corresponding bits in Interrupt Register 2. This register de-
faults to 00.
10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)
The two Interrupt mode registers form a 2-bit code for each Interrupt 2 register function. This code deter-
mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt
condition, or on the continuing occurrence of the interrupt condition. These registers default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
76543210
0
VFIFOM
REUNLOCKM
DETUM
EFTUM
QCHM
UOVWM
76543210
0
VFIFO1
REUNLOCK1
DETU1
EFTU1
QCH1
UOVW1
0
VFIFO0
REUNLOCK0
DETU0
EFTU0
QCH0
UOVW0
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