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參數(shù)資料
| 型號： | CDB8420 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 40/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS8420 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS8420 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC |
| 其它名稱： | 598-1782 |
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DS245F4
45
CS8420
10.16 Receiver Error Mask (11h)
The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis-
ter. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will
appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and
will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set
to 0, the error is considered masked, meaning that its occurrence will not appear in the receiver
error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect
the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they
do not affect the current audio sample even when unmasked. This register defaults to 00.
10.17 Channel Status Data Buffer Control (12h)
BSEL
Selects the data buffer register addresses to contain User data or Channel Status data
0 - Data buffer address space contains Channel Status data (default)
1 - Data buffer address space contains User data
CBMR
Control for the first 5 bytes of channel status “E” buffer
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
(default)
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
DETCI
D to E C-data buffer transfer inhibit bit.
0 - Allow C-data D to E buffer transfers (default)
1 - Inhibit C-data D to E buffer transfers
EFTCI
E to F C-data buffer transfer inhibit bit.
0 - Allow C-data E to F buffer transfers (default)
1 - Inhibit C-data E to F buffer transfers
CAM
C-data buffer control port access mode bit
0 - One byte mode
1 - Two byte mode
CHS
Channel select bit
0 - Channel A information is displayed at the EMPH pin and in the receiver channel
status register. Channel A information is output during control port reads when
CAM is set to 0 (One Byte Mode)
1 - Channel B information is displayed at the EMPH pin and in the receiver channel
status register. Channel B information is output during control port reads when
CAM is set to 0 (One Byte Mode)
76543210
0
QCRCM
CCRCM
UNLOCKM
VM
CONFM
BIPM
PARM
76543210
0
BSEL
CBMR
DETCI
EFTCI
CAM
CHS
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參數(shù)描述 |
|---|---|
| CDB8421 | 功能描述:音頻 IC 開發(fā)工具 2-Ch 32-Bit 192kHz sample rate converte RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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| CDB8952 | 制造商:Cirrus Logic 功能描述:NOT RECOMMENDED FOR NEW DESIGNS - USE CDB8952T - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con |
| CDB8952T | 功能描述:以太網(wǎng)開發(fā)工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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