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參數(shù)資料
| 型號(hào)： | CDB8420 |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 59/94頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS8420 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS8420 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC |
| 其它名稱： | 598-1782 |
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62
DS245F4
CS8420
RMCK - Input Section Recovered Master Clock Output
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).
LOCK - PLL Lock Indicator Output
LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-down
resistor.
Audio Output Interface:
SDOUT - Serial Audio Output Port Data Output
Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.
OSCLK - Serial Audio Output Port Bit Clock Input or Output
Serial bit clock for audio data on the SDOUT pin.
OLRCK - Serial Audio Output Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso).
AES3/SPDIF Transmitter Interface:
TXN, TXP - Differential Line Driver Outputs
Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset
state.
TCBL - Transmit Channel Status Block Start
When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at
all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the current
transmitted sub-frame to be the start of a channel status block.
CUVEN - C, U and V bit Input Enable Mode Input
The CUVEN pin determines how the channel status data, user data and validity bit is input. When CUVEN is low,
Hardware mode 2A is selected, where the EMPH/V, COPY/C and ORIG/U pins are used to enter selected channel
status data. When CUVEN is high, hardware 2B is selected, where the EMPH/V, COPY/C and ORIG/U pins are
used to enter serial C, U and V data.
EMPH/V - Pre-Emphasis Indicator Input or V Bit Input
In mode 2A, EMPH/V low sets the 3 EMPH channel status bits to indicate 50/15
μs pre-emphasis. EMPH/V high
sets the 3 EMPH bits to 000 indicating no pre-emphasis. In mode 2B, EMPH/V low sets the V bit to indicate valid
audio. EMPH/V high sets the V-bit to indicate non-valid audio.
COPY/C - COPY Channel Status Bit Input or C Bit Input
In mode 2A, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing
AES3 type data stream (See Table 9). In mode 2B, COPY/C becomes the direct C bit input data pin.
ORIG/U - ORIG Channel Status Bit Input or U Bit Input
In mode 2A, the ORIG/U pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3
type data stream. (See Table 9). In mode 2B, ORIG/U becomes the direct U bit input data pin.
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