參數(shù)資料
型號: CDB8420
廠商: Cirrus Logic Inc
文件頁數(shù): 69/94頁
文件大?。?/td> 0K
描述: EVALUATION BOARD FOR CS8420
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻,采樣率轉(zhuǎn)換器
嵌入式: 是,MCU,8 位
已用 IC / 零件: CS8420
主要屬性: 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器
次要屬性: 44.1、48、96 kHz 輸出采樣率,AES/EBU,S/PDIF,EIAJ-340,GUI
已供物品:
相關(guān)產(chǎn)品: 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名稱: 598-1782
DS245F4
71
CS8420
13.6
Hardware Mode 5 Description
(AES3 Receiver Only)
Hardware Mode 5 data flow is shown in Figure 28. Audio data is input via the AES3 receiver, and routed to
the serial audio output port. The PRO, COPY, ORIG, EMPH, and AUDIO channel status bits are output on
pins. The decoded C and U bits are also output, clocked by both edges of OLRCK (Master mode only, see
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified
to the serial audio output port.
Start-up options are shown in Table 14, and allow choice of the serial audio output port as a master or slave,
and the serial audio port format. The following pages contain the detailed pin descriptions for Hardware
mode 5.
SDOUT
ORIG
EMPH
Function
LO
-
Serial Output Port is Slave
HI
-
Serial Output Port is Master
-
LO
Serial Output Format OF1
-
LO
HI
Serial Output Format OF2
-
HI
LO
Serial Output Format OF3
-
HI
Serial Output Format OF5
Table 14. Hardware Mode 5 Start-Up Options
Serial
Audio
Output
AES3 Rx
&
Decoder
C&Ubit Data Buffer
RXP
RXN
OLRCK
OSCLK
SDOUT
RMCK
RERR
COPY ORIG
EMPH
RCBL
PRO AUDIO
CHS
DFC0
DFC1
S/AES
VD+
H/S
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
VD+
NVERR
C
U
OMCK
Figure 28. Hardware Mode 5 - AES3 Receiver Only
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