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參數(shù)資料
| 型號： | CDB8420 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 48/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVALUATION BOARD FOR CS8420 |
| 標準包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS8420 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | 44.1、48、96 kHz 輸出采樣率，AES/EBU，S/PDIF，EIAJ-340，GUI |
| 已供物品： | 板 |
| 相關產(chǎn)品： | 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC |
| 其它名稱： | 598-1782 |
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52
DS245F4
CS8420
FILT - PLL Loop Filter *
An RC network should be connected between this pin and ground. Recommended schematic and component val-
ues are given in “PLL Filter” on page 87.
Overall Device Control:
H/S - Hardware or Software Control Mode Select *
The H/S pin determines the method of controlling the operation of the CS8420, and the method of accessing CS
and U data. In Software mode, device control and CS and U data access is primarily via the control port, using a
microcontroller. In Hardware mode, alternate modes and access to CS and U data is provided by pins. This pin
should be permanently tied to VD+ or DGND.
RST - Reset Input *
When RST is low, the CS8420 enters a low-power mode and all internal states are reset. On initial power-up, RST
must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is
particularly true in Hardware mode with multiple CS8420 devices, where synchronization between devices is impor-
tant.
INT - Interrupt Output
The INT output pin indicates errors and key events during the operation of the CS8420. All bits affecting INT are
maskable via control registers. The condition(s) that initiated interrupt are readable via a control register. The polarity
of the INT output, as well as selection of a standard or open-drain output, is set via a control register. Once set true,
the INT pin goes false only after the interrupt status registers have been read, and the interrupt status bits have re-
turned to zero.
Audio Input Interface:
SDIN - Serial Audio Input Port Data Input
Audio data serial input pin.
ISCLK - Serial Audio Input Port Bit Clock Input or Output
Serial bit clock for audio data on the SDIN pin.
ILRCK - Serial Audio Input Port Left/Right Clock Input or Output
Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs
Differential line receiver inputs, carrying AES3-type data.
RERR - Receiver Error Indicator
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per
sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phase
coding error, confidence, QCRC and CCRC errors, as well as loss of lock in the PLL. Optionally, each condition may
be masked from affecting the RERR pin using the Receiver Error Mask Register. The RERR pin tracks the status
of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when
all unmasked errors go away.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CDB8421 | 功能描述:音頻 IC 開發(fā)工具 2-Ch 32-Bit 192kHz sample rate converte RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB8422 | 功能描述:界面開發(fā)工具 Eval Bd 192kHz SRC S/PDIF Receiver RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CDB8427 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 96kHz Dig. Audio Transcvr RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB8952 | 制造商:Cirrus Logic 功能描述:NOT RECOMMENDED FOR NEW DESIGNS - USE CDB8952T - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con |
| CDB8952T | 功能描述:以太網(wǎng)開發(fā)工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
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