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| 型號(hào)： | COP8CBR9HLQ8 |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 51/111頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 8BIT 44LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 37 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-WFQFN 裸露焊盤(pán) |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | *COP8CBR9HLQ8 COP8CBR9HLQ8CT |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Any time the IDLE Timer period is changed there is the possibility of generating a spurious IDLE Timer
interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to changing
the value of the ITSEL bits of the ITMR Register and then clear the T0PND bit before attempting to
synchronize operation to the IDLE Timer.
5.11.2 TIMER T1, TIMER T2, AND TIMER T3
The device has a set of three powerful timer/counter blocks, T1, T2, and T3. Since T1, T2 and T3 are
identical, except for the high speed operation of T2 and T3, all comments are equally applicable to any of
the three timer blocks which will be referred to as Tx. Differences between the timers will be specifically
noted.
Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload/capture registers,
RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I/O
required by the timer block, while the pin TxB is an input to the timer block. The timer block has three
operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture
mode.
The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation.
5.11.2.1 Timer Operating Speeds
Each of the Tx timers, except T1, have the ability to operate at either the instruction cycle frequency (low
speed) or the internal clock frequency (MCLK). For 10 MHz CKI, the instruction cycle frequency is 2 MHz
and the internal clock frequency is 20 MHz. This feature is controlled by the High Speed Timer Control
Register, HSTCR. Its format is shown below. To place a timer, Tx, in high speed mode, set the
appropriate TxHS bit to 1. For low speed operation, clear the appropriate TxHS bit to 0. This register is
cleared to 00 on Reset.
HSTCR
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
1
0
0
T3HS
T2HS
5.11.2.2 Mode 1. Processor Independent PWM Mode
One of the timer's operating modes is the Processor Independent PWM mode. In this mode, the timers
generate a “Processor Independent” PWM signal because once the timer is set up, no more action is
required from the CPU which translates to less software overhead and greater throughput. The user
software services the timer block only when the PWM parameters require updating. This capability is
provided by the fact that the timer has two separate 16-bit reload registers. One of the reload registers
contains the “ON” time while the other holds the “OFF” time. By contrast, a microcontroller that has only a
single reload register requires an additional software to update the reload value (alternate between the on-
time/off-time).
The timer can generate the PWM output with the width and duty cycle controlled by the values stored in
the reload registers. The reload registers control the countdown values and the reload values are
automatically written into the timer when it counts down through 0, generating interrupt on each reload.
Under software control and with minimal overhead, the PWM outputs are useful in controlling motors,
triacs, the intensity of displays, and in providing inputs for data acquisition and sine wave generators.
In this mode, the timer Tx counts down at a fixed rate of tC (T2 and T3 may be selected to operate from
MCLK). Upon every underflow the timer is alternately reloaded with the contents of supporting registers,
RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA.
Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the
register RxB.
Figure 5-10 shows a block diagram of the timer in PWM mode.
44
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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