參數(shù)資料
型號(hào): COP8CBR9HLQ8
廠商: National Semiconductor
文件頁(yè)數(shù): 99/111頁(yè)
文件大?。?/td> 0K
描述: IC MCU CMOS 8BIT 44LLP
標(biāo)準(zhǔn)包裝: 1
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-WFQFN 裸露焊盤(pán)
包裝: 剪切帶 (CT)
其它名稱: *COP8CBR9HLQ8
COP8CBR9HLQ8CT
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.18 Memory Map
All RAM, ports and registers (except A and PC) are mapped into data memory address space.
Address
Contents(1)
S/ADD REG
0000 to 006F
On-Chip RAM bytes (112 bytes)
0070 to 007F
Unused RAM Address Space (Reads As All Ones)
xx80 to xx90
Unused RAM Address Space (Reads Undefined Data)
xx90
Port E Data Register
xx91
Port E Configuration Register
xx92
Port E Input Pins (Read Only)
xx93
Reserved for Port E
xx94
Port F Data Register
xx95
Port F Configuration Register
xx96
Port F Input Pins (Read Only)
xx97
Reserved for Port F
xx98 to xx9F
Reserved
xxA0
Port A Data Register
xxA1
Port A Configuration Register
xxA2
Port A Input Pins (Read Only)
xxA3
Reserved for Port A
xxA4
Port B Data Register
xxA5
Port B Configuration Register
xxA6
Port B Input Pins (Read Only)
xxA7
Reserved for Port B
xxA8
ISP Address Register Low Byte (ISPADLO)
xxA9
ISP Address Register High Byte (ISPADHI)
xxAA
ISP Read Data Register (ISPRD)
xxAB
ISP Write Data Register (ISPWR)
xxAC
Reserved
xxAD
Reserved
xxAE
Reserved
xxAF
High Speed Timers Control Register (HSTCR)
xxB0
Timer T3 Lower Byte
xxB1
Timer T3 Upper Byte
xxB2
Timer T3 Autoload Register T3RA Lower Byte
xxB3
Timer T3 Autoload Register T3RA Upper Byte
xxB4
Timer T3 Autoload Register T3RB Lower Byte
xxB5
Timer T3 Autoload Register T3RB Upper Byte
xxB6
Timer T3 Control Register
xxB7
Reserved
xxB8
USART Transmit Buffer (TBUF)
xxB9
USART Receive Buffer (RBUF)
xxBA
USART Control and Status Register (ENU)
xxBB
USART Receive Control and Status Register (ENUR)
xxBC
USART Interrupt and Clock Source Register (ENUI)
xxBD
USART Baud Register (BAUD)
xxBE
USART Prescale Select Register (PSR)
(1)
Reading memory locations 0070H–007FH (Segment 0) will return all ones. Reading unused memory
locations 0080H–0093H (Segment 0) will return undefined data. Reading memory locations from other
Segments (i.e., Segment 8, Segment 9, … etc.) will return undefined data.
88
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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