- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3791 > COP8CBR9HLQ8 (National Semiconductor)IC MCU CMOS 8BIT 44LLP PDF資料下載
參數(shù)資料
| 型號： | COP8CBR9HLQ8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 93/111頁 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 8BIT 44LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 37 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-WFQFN 裸露焊盤 |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | *COP8CBR9HLQ8 COP8CBR9HLQ8CT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁當(dāng)前第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Table 5-27. WATCHDOG Service Window Select (continued)
Clock
Service Window
WDSVR
Monitor
for High Speed Mode
for Dual Clock & Low Speed Modes
Bit 7
Bit 6
Bit 0
(Lower-Upper Limits)
X
1
Clock Monitor Enabled
5.16.1 CLOCK MONITOR
The Clock Monitor aboard the device can be selected or deselected under program control. The Clock
Monitor is ensured not to reject the clock if the instruction cycle clock (1/tC) is greater or equal to 5 kHz.
This equates to a clock input rate on the selected oscillator of greater or equal to 25 kHz.
5.16.2 WATCHDOG/CLOCK MONITOR OPERATION
The WATCHDOG is enabled by bit 2 of the Option register. When this Option bit is 0, the WATCHDOG is
enabled and pin G1 becomes the WATCHDOG output with a weak pull-up.
The WATCHDOG and Clock Monitor are disabled during reset. The device comes out of reset with the
WATCHDOG armed, the WATCHDOG Window Select bits (bits 6, 7 of the WDSVR Register) set, and the
Clock Monitor bit (bit 0 of the WDSVR Register) enabled. Thus, a Clock Monitor error will occur after
coming out of reset, if the instruction cycle clock frequency has not reached a minimum specified value,
including the case where the oscillator fails to start.
The WDSVR register can be written to only once after reset and the key data (bits 5 through 1 of the
WDSVR Register) must match to be a valid write. This write to the WDSVR register involves two
irrevocable choices: (i) the selection of the WATCHDOG service window (ii) enabling or disabling of the
Clock Monitor. Hence, the first write to WDSVR Register involves selecting or deselecting the Clock
Monitor, select the WATCHDOG service window and match the WATCHDOG key data. Subsequent
writes to the WDSVR register will compare the value being written by the user to the WATCHDOG service
window value, the key data and the Clock Monitor Enable (all bits) in the WDSVR Register. Table 5-28
shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before the upper limit of the service window expires.
The WATCHDOG may not be serviced more than once in every lower limit of the service window.
When jumping to the boot ROM for ISP and virtual E2 operations, the hardware will disable the lower
window error and perform an immediate WATCHDOG service. The ISP routines will service the
WATCHDOG within the selected upper window. The ISP routines will service the WATCHDOG
immediately prior to returning execution back to the user's code in flash. Therefore, after returning to flash
memory, the user can service the WATCHDOG anytime following the return from boot ROM, but must
service it within the selected upper window to avoid a WATCHDOG error.
The WATCHDOG has an output pin associated with it. This is the WDOUT pin, on pin 1 of the port G.
WDOUT is active low. The WDOUT pin has a weak pull-up in the inactive state. Upon triggering the
WATCHDOG, the logic will pull the WDOUT (G1) pin low for an additional 16–32 cycles after the signal
level on WDOUT pin goes below the lower Schmitt trigger threshold. After this delay, the device will stop
forcing the WDOUT output low. The WATCHDOG service window will restart when the WDOUT pin goes
high.
A WATCHDOG service while the WDOUT signal is active will be ignored. The state of the WDOUT pin is
not ensured on reset, but if it powers up low then the WATCHDOG will time out and WDOUT will go high.
The Clock Monitor forces the G1 pin low upon detecting a clock frequency error. The Clock Monitor error
will continue until the clock frequency has reached the minimum specified value, after which the G1 output
will go high following 16–32 clock cycles. The Clock Monitor generates a continual Clock Monitor error if
the oscillator fails to start, or fails to reach the minimum specified frequency. The specification for the
Clock Monitor is as follows:
1/tC > 5 kHz—No clock rejection.
82
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9S08SH32VTJ | MCU 8BIT 32K FLASH 20-TSSOP |
| MC9S08SH32VTG | MCU 8BIT 32K FLASH 16-TSSOP |
| MC9S08SH16VWL | MCU 8BIT 16K FLASH 28-SOIC |
| MC9S08SH16VTL | MCU 8BIT 16K FLASH 28-TSSOP |
| MC9S08SH16VTG | MCU 8BIT 16K FLASH 16-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP8CBR9HVA8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8CBR9HVA8/NOPB | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8CBR9IMT8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8CBR9IMT8/NOPB | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| COP8CBR9KMT8 | 功能描述:IC MCU EEPROM 8BIT 32K 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:COP8™ 8C 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。