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參數(shù)資料
| 型號： | COP8CBR9HLQ8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 70/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 8BIT 44LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 37 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-WFQFN 裸露焊盤 |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | *COP8CBR9HLQ8 COP8CBR9HLQ8CT |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
PE = 0
Indicates no Parity Error has been detected since the last time the ENUR register was read.
PE = 1
Indicates the occurrence of a Parity Error.
BD: Flags a line break.
BD = 0
Indicates no Line Break has been detected since the last time the ENUR register was read.
BD = 1
Indicates the occurrence of a Line Break.
RBIT9: Contains the ninth data bit received when the USART is operating with nine data bits per frame.
Read only, cleared on reset.
ATTN: ATTENTION Mode is enabled while this bit is set. This bit is cleared automatically on receiving a
character with data bit nine set. Read/Write, cleared on reset.
XMTG: This bit is set to indicate that the USART is transmitting. It gets reset at the end of the last frame
(end of last Stop bit). Read only, cleared on reset.
RCVG: This bit is set high whenever a framing error or a break detect occurs and goes low when RDX
goes high. Read only, cleared on reset.
ENUI—USART INTERRUPT AND CLOCK SOURCE REGISTER (Address at 0BC)
STP2
BRK
ETDX
SSEL
XRCLK
XTCLK
ERI
ETI
Bit 7
Bit 0
STP2: This bit programs the number of Stop bits to be transmitted. Read/Write, cleared on reset.
STP2 = 0
One Stop bit transmitted.
STP2 = 1
Two Stop bits transmitted.
BRK: Holds TDX (USART Transmit Pin) low to generate a Line Break. Timing of the Line Break is under
software control.
ETDX: TDX (USART Transmit Pin) is the alternate function assigned to Port L pin L2; it is selected by
setting ETDX bit.
SSEL: USART mode select. Read only, cleared on reset.
SSEL = 0
Asynchronous Mode.
SSEL = 1
Synchronous Mode.
XRCLK: This bit selects the clock source for the receiver section. Read/Write, cleared on reset.
XRCLK = 0
The clock source is selected through the PSR and BAUD registers.
XRCLK = 1
Signal on CKX (L1) pin is used as the clock.
XTCLK: This bit selects the clock source for the transmitter section. Read/Write, cleared on reset.
XTCLK = 0
The clock source is selected through the PSR and BAUD registers.
XTCLK = 1
Signal on CKX (L1) pin is used as the clock.
ERI: This bit enables/disables interrupt from the receiver section. Read/Write, cleared on reset.
ERI = 0
Interrupt from the receiver is disabled.
ERI = 1
Interrupt from the receiver is enabled.
ETI: This bit enables/disables interrupt from the transmitter section. Read/Write, cleared on reset.
ETI = 0
Interrupt from the transmitter is disabled.
ETI = 1
Interrupt from the transmitter is enabled.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
61
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