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| 型號(hào)： | CR16HCT5VJE8Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 100/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE8Y |
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100
Note:
The canceled message can be delayed by a TX re-
quest of a buffer with a higher priority. During TX_BUSY high,
the user cannot change the contents of the message buffer
object. In all cases writing to the BUSY bit will be ignored.
20.6.2
CR16CAN is able to generate a stream of scheduled mes-
sages without releasing the bus between two messages so
that an optimized performance can be achieved. It will arbi-
trate for the bus right after sending the previous message
and will only release the bus due to a lost arbitration.
If more than one buffer is scheduled for transmission, the pri-
ority is built by the message buffer number and the priority
code in the CNSTAT register. The 8-bit value of the priority is
combined by the 4-bit TXPRI value and the 4-bit buffer num-
ber (0...14) as shown below. The lowest resulting number re-
sults in the highest transmit priority.
Transmit Priority
Table 22 shows the transmit priority configuration if the prior-
ity is set to TXPRI = 0 for all transmit buffers:
Table 22
Transmit Priority (TXPRI=0)
Table 23 shows the transmit priority configuration if TXPRI is
different from the buffer number:
Table 23
Transmit Priority (TXPRI not 0)
Note:
If two buffers have the same priority (PRI), the buffer
with the lower buffer number will have the higher priority.
20.6.3
The transmission of a CAN message has to be executed as
follows (see also Figure 65)
1. Configure CNSTAT status field as TX_NOT_ACTIVE. If
the status is TX_BUSY, a previous transmit request is
still pending and the user has no access to the data con-
tents of the buffer. In that case the user may choose to
wait until the buffer becomes available again as shown.
Other options are to exit from the update routine until the
buffer has been transmitted with an interrupt generated,
or the transmission is aborted by an error.
2. Load buffer identifier & data registers. (For remote
frames the RTR bit of the identifier needs to be set and
loading data bytes can be omitted.)
3. Configure CNSTAT status field to the desired value:
— TX_ONCE to trigger the transmission process of a sin-
gle frame.
— TX_ONCE_RTR to trigger the transmission of a single
data frame and then wait for a received remote frame
to trigger consecutive data frames.
— TX_RTR waits for a remote frame to trigger the trans-
mission of a data frame.
Writing TX_ONCE or TX_ONCE_RTR in the CNSTAT status
field will set the internal transmit request for the CR16CAN.
If a buffer is configured as TX_RTR and a remote frame is re-
ceived, the data contents of the addressed buffer will be
transmitted automatically without further CPU activity.
Transmit Procedure
TXPRI
Buffer
Number
PRI
TX Priority
0
0
:
:
0
0
1
:
:
0
1
:
:
highest
:
:
14
14
lowest
TXPRI
Buffer
Number
PRI
TX Priority
14
0
224
lowest
13
1
209
12
2
194
11
3
179
10
4
164
9
5
149
8
6
134
7
7
119
6
8
104
5
9
89
4
10
74
3
11
59
TXPRI
BUFFER #
2
12
44
1
13
29
0
14
14
highest
Table 23
Transmit Priority (TXPRI not 0)
TXPRI
Buffer
Number
PRI
TX Priority
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| CR16HCT5VJE9Y | Microcontroller |
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| CR16HCT9VJE7Y | Microcontroller |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CR16HCT5VJE9Y | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microcontroller |
| CR16HCT5VJEXY | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microcontroller |
| CR16HCT9VJE7Y | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Microcontroller |
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