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| 型號(hào)： | CR16HCT5VJE8Y |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 91/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5VJE8Y |
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Interframe Space
Data and remote frames are separated from every preceding
frame (data, remote, error and overload frames) by the inter-
frame space (see Figure 50). Error and overload frames are
not preceded by an interframe space; they can be transmit-
ted as soon as the condition occurs. The interframe space
consists of a minimum of three bit fields depending on the er-
ror state of the node.
20.2.2
There are multiple mechanisms in the CAN protocol to detect
errors and inhibit erroneous modules from disabling all bus
activities. Each CAN module includes two error counters, a
receive and a transmit error counter, for error management.
Error Detection and Management
Error Types
The following errors can be detected:
— Bit Error
A CAN device which is currently transmitting also mon-
itors the bus. If the monitored bit value is different from
the transmitted bit value, a bit error is detected. How-
ever, the reception of a ‘dominant’ bit instead of a ‘re-
cessive’ bit during the transmission of a passive error
flag, during the stuffed bit stream of the arbitration field
or during the acknowledge slot is not interpreted as a
bit error.
— Stuff Error
A stuff error is detected if the bit level after 6 consecu-
tive bit times has not changed in a message field that
has to be coded according to the bit stuffing method.
— Form Error
A form error is detected, if a fixed frame bit (e.g., CRC
delimiter, ACK delimiter) does not have the specified
value. For a receiver, a ‘dominant’ bit during the last bit
of End of Frame does not constitute a frame error.
— Bit CRC Error
A CRC error is detected if the remainder of the CRC
calculation of a received CRC polynomial is non-zero.
— Acknowledgment Error
An acknowledgment error is detected whenever a
transmitting node does not get an acknowledgment
from any other node (i.e., when the transmitter does
not receive a ‘dominant’ bit during the ACK frame)
Error States
The device can be in one of four states with respect to error
handling (see Figure 51)
— Synchronize
Once the CR16CAN is enabled, it goes into a synchro-
nization state to synchronize with the bus by waiting for
11 consecutive recessive bits. After that the CR16CAN
becomes error active and can participate in the bus
communication. This state must also be entered after
waking-up the device via the Multi-Input Wake-Up fea-
ture. See System Start-Up and Multi-Input Wake-Up on
page 115.
— Error active
An error active unit can participate in bus communica-
tion and may send an active (‘dominant’) error flag.
— Error Warning
The Error Warning state is a sub-state of Error Active
to indicate a heavily disturbed bus. The CR16CAN be-
haves as in Error Active mode. The device is reset into
the Error Active mode if the value of both counters is
less than 96.
— Error passive
An error passive unit can participate in bus communi-
cation. However, if the unit detects an error it is not al-
lowed to send an active error flag. The unit sends only
a passive (‘recessive’) error flag. A device is error pas-
sive when the transmit error counter or the receive er-
ror counter is greater than 127. A device becoming
error passive will send an active error flag. An error
passive device becomes error active again when both
transmit and receive error counter are less than 128.
— Bus off
A unit that is bus off has the output drivers disabled,
i.e., it does not participate in any bus activity. A device
is bus off when the transmit error counter is greater
than 255. A bus off device will become error active
again after monitoring 128*11 ‘recessive’ bits (includ-
ing bus idle) on the bus. When the device goes from
‘bus off’ to ‘error active’, both error counters will have
the value ‘0’.
r r r r
r
r
r
r
3
8
r r r r
r
r r
r
d
r
INT
SUSPEND
TRANSMIT
BUS IDLE
DATA FRAME OR
REMOTE FRAME
INT = Intermission
Suspend Transmission is only for error passive nodes.
INTERFRAME SPACE
r
r
r r r
r
S
ANY FRAME
Note:
d = dominant
r = recessive
Figure 50.
CAN Interframe Space
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| CR16HCT5VJE9Y | Microcontroller |
| CR16HCT9 | |
| CR16HCT9VJE7 | Microcontroller |
| CR16HCT9VJE7Y | Microcontroller |
| CR16HCT9VJE8 | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCT5VJE9Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT5VJEXY | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller |
| CR16HCT9VJE7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCT9VJE7Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
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