參數(shù)資料
型號(hào): CR16HCT5VJE8Y
英文描述: Microcontroller
中文描述: 微控制器
文件頁(yè)數(shù): 6/157頁(yè)
文件大小: 1256K
代理商: CR16HCT5VJE8Y
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
www.national.com
6
3.5
The Interrupt Control Unit (ICU31L) receives interrupt re-
quests from internal and external sources and generates in-
terrupts to the CPU. An interrupt is an event that temporarily
stops the normal flow of program execution and causes a
separate interrupt service routine to be executed. After the in-
terrupt is serviced, CPU execution continues with the next in-
struction in the program following the point of interruption.
Interrupts from the timers, USARTs, MICROWIRE/SPI inter-
face, multi-input wake-up, and A/D converter are all
maskable interrupts; they can be enabled or disabled by the
software. There are 32 of these maskable interrupts, orga-
nized into 32 predetermined levels of priority.
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI in-
put pin.
INTERRUPTS
3.6
The Multi-Input Wake-Up (MIWU16) module can be used for
either of two purposes: to provide inputs for waking up (exit-
ing) from the HALT, IDLE, or Power Save mode; or to provide
general-purpose edge-triggered maskable interrupts from
external sources. This 16-channel module generates four
programmable interrupts to the CPU based on the signals re-
ceived on its 16 input channels. Channels can be individually
enabled or disabled, and programmed to respond to positive
or negative edges.
MULTI-INPUT WAKE-UP
3.7
The Dual Clock and Reset (CLK2RES) module generates a
high-speed main system clock from an external crystal net-
work. It also provides the main system reset signal and a
power-on reset function.
This module also generates a slow system clock (32.768
kHz) from another external crystal network. The slow clock is
used for operating the device in power-save mode. Without a
32.768kHz external crystal network, the low speed system
clock can be derived from the high speed clock by a prescal-
er.
Also, two independent clocks divided down from the high
speed clock are available on output pins.
DUAL CLOCK AND RESET
3.8
The Power Management Module (PMM) improves the effi-
ciency of the CR16MCS9/CR16MCS5 and CR16HCS9/
CR16HCS5 by changing the operating mode and therefore
the power consumption according to the required level of ac-
tivity.
The CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
can operate in any of four power modes:
— Active: The CR16MCS9/CR16MCS5 and CR16HCS9/
CR16HCS5 operate at full speed using the high-fre-
quency clock. All devices function are fully operational.
— Power Save: The device operates at reduced speed
using the slow clock. The CPU and some modules can
continue to operate at this low speed.
— IDLE: The device is inactive except for the Power Man-
agement Module and Timing and Watchdog Module,
which continue to operate using the slow clock.
POWER MANAGEMENT
— HALT: The device is inactive but still retains its internal
state (RAM and register contents).
3.9
The Multi-Function Timer (MFT16) module contains two in-
dependent timer/counter units called MFT1 and MFT2, each
containing a pair of 16-bit timer/counter registers. Each timer/
counter unit can be configured to operate in any of the follow-
ing modes:
— Processor-Independent
(PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a gener-
al-purpose timer/counter.
— Dual Input Capture mode, which measures the
elapsed time between occurrences of external events,
and which also provides a general-purpose timer/
counter.
— Dual Independent Timer mode, which generates sys-
tem timing signals or counts occurrences of external
events.
— Single Input Capture and Single Timer mode, which
provides one external event counter and one system
timer.
MULTI-FUNCTION TIMER
Pulse
Width
Modulation
3.10
The Versatile Timer Unit (VTU) module contains four inde-
pendent timer subsystems, each operating in either dual 8-bit
PWM configuration, as a single 16-bit PWM timer, or a 16-bit
counter with two input capture channels. Each of the four tim-
er subsystems offer an 8-bit clock prescaler to accommodate
a wide range of frequencies.
VERSATILE TIMER UNIT
3.11
The Timing and Watchdog Module (TWM) generates the
clocks and interrupts used for timing periodic functions in the
system. It also provides Watchdog protection against soft-
ware errors. The module operates on the slow system clock.
The real-time timer can generate a periodic interrupt to the
CPU at a software-programmed interval. This can be used
for real-time functions such as a time-of-day clock. The real-
time timer can trigger a wake-up condition from power-save
mode via the Multi-Input Wake-Up module.
The Watchdog is designed to detect program execution er-
rors such as an infinite loop or a “runaway” program. Once
Watchdog operation is initiated, the application program
must periodically write a specific value to a Watchdog regis-
ter, within specific time intervals. If the software fails to do so,
a Watchdog error is triggered, which resets the device.
REAL-TIME TIMER AND WATCHDOG
3.12
The USART supports a wide range of programmable baud
rates and data formats, and handles parity generation and
several error detection schemes. The baud rate is generated
on-chip, under software control.
There are two independent USARTs in the device and they
offer a wake-up condition from the power-save mode via the
Multi-Input Wake-Up module.
USART
3.13
The MICROWIRE/SPI (MWSPI) interface module supports
synchronous serial communications with other devices that
MICROWIRE/SPI
相關(guān)PDF資料
PDF描述
CR16HCT5VJE9Y Microcontroller
CR16HCT9
CR16HCT9VJE7 Microcontroller
CR16HCT9VJE7Y Microcontroller
CR16HCT9VJE8 Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CR16HCT5VJE9Y 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
CR16HCT5VJEXY 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller
CR16HCT9 制造商:NSC 制造商全稱:National Semiconductor 功能描述:CR16MCT9/CR16MCT5/CR16HCT9/CR16HCT5 16-Bit Reprogrammable/ROM Microcontroller
CR16HCT9VJE7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller
CR16HCT9VJE7Y 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller