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參數(shù)資料
| 型號(hào)： | CS61884-IRZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 20/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LN INTERF T1/E1/J1 160-LFBGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 8 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 功率（瓦特）： | 1.73W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 160-TFGBA（13x13） |
| 包裝： | 散裝 |
| 包括： | AMI 編碼器和解碼器，B8ZS 編碼器和解碼器，HDB3 編碼器和解碼器，LOS 檢測(cè) |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1717 |
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CS61884
DS485F3
27
RPOS/RDATA pin. When bipolar violations are
detected by the decoder, the RNEG/BPV pin is as-
serted “High”. This pin is driven “high” one RCLK
period for every bipolar violation that is not part of
the zero substitution rules. Unipolar mode is en-
tered by holding the TNEG pin “High” for more
than 16 MCLK cycles.
In hardware mode, the B8ZS/HDB3/AMI encod-
ing/Decoding is activated via the CODEN pin. In
host mode, the Global Control Register (0Fh)
(See Section 14.16 on page 38) is used to select the
encoding/decoding for all channels.
10.3 RZ Output Mode
In this mode the RTIP and RRING inputs are sliced
to data values that are output on RPOS and RNEG.
This mode is used in applications that have clock
recovery circuitry external to the LIU. To support
external clock recovery, the RPOS and RNEG out-
puts are XORed and output on an edge of RCLK.
This mode is entered when MCLK is tied high.
NOTE: The valid RCLK edge of the RPOS/RNEG data
is controlled by the CLKE pin.
10.4 Receiver Powerdown/High-Z
All eight receivers are powered down when MCLK
is held low. In addition, this will force the RCLK,
RPOS, and RNEG outputs into a high impedance
state.
10.5 Loss-of-Signal (LOS)
The CS61884 makes use of both analog and digital
LOS detection circuitry that is compliant to the lat-
est specifications. During T1/J1 operation ANSI
T1.231 is supported and in E1 operation mode, ei-
ther ITU G.775 or ETSI 300 233 is supported. The
LOS condition in E1 mode is changed from ITU
G.775 to ETSI 300 233 in the LOS/AIS Mode En-
The LOS detector increments a counter each time a
zero is received, and resets the counter each time a
one “mark” is received. Depending on LOS detec-
tion mode, the LOS signal is set when a certain
number of consecutive zeros are received. In
Clock/Data recovery mode, this forces the recov-
ered clock to be replaced by MCLK at the RCLK
output. In addition the RPOS/RNEG outputs are
forced “high” for the length of the LOS period ex-
cept when local and analog loopback are enabled.
Upon exiting LOS, the recovered clock replaces
MCLK on the RCLK output. In Data recovery
mode, RCLK is not replaced by MCLK when LOS
is active. The LOS detection modes are summa-
rized below.
NOTE: T1.231, G.775 and ETSI 300 233 are all avail-
able in host mode, but in hardware mode only
ETSI 300 233 and T1.231 are available.
ANSI T1.231 (T1/J1 Mode Only) - LOS is detect-
ed if the receive signal is less than 200 mV for a pe-
riod of 176 continuous pulse periods. The channel
exits the LOS condition when the pulse density ex-
ceeds 12.5% over 176 pulse periods since the re-
ceipt of the last pulse. An incoming signal with a
pulse amplitude exceeding 250 mV will cause a
pulse transition on the RPOS/RDATA or RNEG
outputs.
ITU G.775 (E1 Mode Only) - LOS is declared
when the received signal level is less than 200 mV
for 32 consecutive pulse periods (typical). The de-
vice exits LOS when the received signal achieves
12.5% ones density with no more than 15 consecu-
tive zeros in a 32 bit sliding window and the signal
level exceeds 250 mV.
ETSI 300 233 (E1 Host Mode Only) - The LOS
indicator becomes active when the receive signal
level drops below 200 mV for more than 2048
pulse periods (1 msec). The channel exits the LOS
state when the input signal exceeds 250 mV and
has transitions for more than 32 pulse periods
(16
μsec). This LOS detection method can only be
selected while in host mode.
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