參數(shù)資料
型號(hào)： CS61884-IRZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 9/72頁
文件大?。?/td> 0K
描述： IC LN INTERF T1/E1/J1 160-LFBGA
標(biāo)準(zhǔn)包裝： 126
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 3.14 V ~ 3.47 V
功率（瓦特）： 1.73W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-LFBGA
供應(yīng)商設(shè)備封裝： 160-TFGBA（13x13）
包裝： 散裝
包括： AMI 編碼器和解碼器，B8ZS 編碼器和解碼器，HDB3 編碼器和解碼器，LOS 檢測(cè)
產(chǎn)品目錄頁面： 759 (CN2011-ZH PDF)
其它名稱： 598-1717
CS61884
DS485F3
17
RCLK0
39
P1
O
Receive Clock Output Port 0
- When MCLK is active, this pin outputs the recovered clock
from the signal input on RTIP and RRING. In the event of
LOS, the RCLK output transitions from the recovered clock
to MCLK.
- If MCLK is held “High”, the clock recovery circuitry is dis-
abled and the RCLK output is driven by the XOR of RNEG
and RPOS.
- If MCLK is held “Low”, this output is in a high-impedance
state.
RPOS0/RDATA0
RNEG0/BPV0
40
41
P2
P3
O
Receive Positive Pulse/ Receive Data Output Port 0
Receive Negative Pulse/Bipolar Violation Output Port 0
The function of the RPOS/RDATA and RNEG/BPV outputs
are determined by whether Unipolar, Bipolar, or RZ input
mode has been selected. During LOS, the RPOS/RNEG
outputs will remain active.
NOTE: The RPOS/RNEG outputs can be High-Z by holding
MCLK Low.
Bipolar Output Mode - When configured for Bipolar opera-
tion, NRZ Data is recovered from RTIP/RRING and output
on RPOS/RNEG. A high signal on RPOS or RNEG corre-
spond to the receipt of a positive or negative pulse on
RTIP/RRING respectively. The RPOS/RNEG outputs are
valid on the falling or rising edge of RCLK as configured by
CLKE.
Unipolar Output Mode - When unipolar mode is activated,
the recovered data is output on RDATA. The decoder sig-
nals bipolar Violations on the RNEG/BPV pin.
RZ Output Mode - In this mode, the RPOS/RNEG pins
output RZ data recovered by slicing the signal present on
RTIP/RRING. A positive pulse on RTIP with respect to
RRING generates a logic 1 on RPOS; a positive pulse on
RRING with respect to RTIP generates a logic 1 on RNEG.
The polarity of the output on RPOS/RNEG is selectable us-
ing the CLKE pin. In this mode, external circuitry is used to
recover clock from the received signal.
TCLK1
29
L1
I
Transmit Clock Input Port 1
TPOS1/TDATA1
30
L2
I
Transmit Positive Pulse/Transmit Data Input Port 1
TNEG1/UBS1
31
L3
I
Transmit Negative Pulse/Unipolar-Bipolar Select Port 1
RCLK1
32
M1
O
Receive Clock Output Port 1
RPOS1/RDATA1
33
M2
O
Receive Positive Pulse/ Receive Data Output Port 1
RNEG1/BPV1
34
M3
O
Receive Negative Pulse/Bipolar Violation Output Port 1
TCLK2
81
L14
I
Transmit Clock Input Port 2
TPOS2/TDATA2
80
L13
I
Transmit Positive Pulse/Transmit Data Input Port 2
TNEG2/UBS2
79
L12
I
Transmit Negative Pulse/Unipolar-Bipolar Select Port 2
SYMBOL
LQFP
LFBGA
TYPE
DESCRIPTION
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