16.1.4 Select-DR-Scan This is a temporary controller state. 16.1.5 Capture-DR In this state, the Boundary Scan Regist" />
參數(shù)資料
型號(hào): CS61884-IRZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 41/72頁(yè)
文件大?。?/td> 0K
描述: IC LN INTERF T1/E1/J1 160-LFBGA
標(biāo)準(zhǔn)包裝: 126
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 3.14 V ~ 3.47 V
功率(瓦特): 1.73W
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 160-LFBGA
供應(yīng)商設(shè)備封裝: 160-TFGBA(13x13)
包裝: 散裝
包括: AMI 編碼器和解碼器,B8ZS 編碼器和解碼器,HDB3 編碼器和解碼器,LOS 檢測(cè)
產(chǎn)品目錄頁(yè)面: 759 (CN2011-ZH PDF)
其它名稱(chēng): 598-1717
CS61884
46
DS485F3
16.1.4 Select-DR-Scan
This is a temporary controller state.
16.1.5 Capture-DR
In this state, the Boundary Scan Register captures
input pin data if the current instruction is EXTEST
or SAMPLE/PRELOAD.
16.1.6 Shift-DR
In this controller state, the active test data register
connected between TDI and TDO, as determined
by the current instruction, shifts data out on TDO
on each rising edge of TCK.
16.1.7 Exit1-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.8 Pause-DR
The pause state allows the test controller to tempo-
rarily halt the shifting of data through the current
test data register.
16.1.9 Exit2-DR
This is a temporary state. The test data register se-
lected by the current instruction retains its previous
value.
16.1.10 Update-DR
The Boundary Scan Register is provided with a
latched parallel output to prevent changes while
data is shifted in response to the EXTEST and
SAMPLE/PRELOAD instructions. When the TAP
controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel
output of this register from the shift-register path
on the falling edge of TCK. The data held at the
latched parallel output changes only in this state.
1
0
Test-Logic-Reset
Run-Test/Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select- I R-Scan
Capture- IR
Shift- IR
Exit1- IR
Pause- IR
Exit2- IR
Update- I R
0
11
1
11
1
11
1
0
00
0
1
0
Figure 16. TAP Controller State Diagram
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