14.9 LOS " />
參數(shù)資料
型號: CS61884-IRZ
廠商: Cirrus Logic Inc
文件頁數(shù): 30/72頁
文件大?。?/td> 0K
描述: IC LN INTERF T1/E1/J1 160-LFBGA
標(biāo)準(zhǔn)包裝: 126
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 8
電源電壓: 3.14 V ~ 3.47 V
功率(瓦特): 1.73W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-LFBGA
供應(yīng)商設(shè)備封裝: 160-TFGBA(13x13)
包裝: 散裝
包括: AMI 編碼器和解碼器,B8ZS 編碼器和解碼器,HDB3 編碼器和解碼器,LOS 檢測
產(chǎn)品目錄頁面: 759 (CN2011-ZH PDF)
其它名稱: 598-1717
CS61884
36
DS485F3
14.7 LOS Interrupt Enable Register (06h)
14.8 DFM Interrupt Enable Register (07h)
14.9 LOS Interrupt Status Register (08h)
14.10 DFM Interrupt Status Register (09h)
14.11 Software Reset Register (0Ah)
14.12 Performance Monitor Register (0Bh)
BIT
NAME
Description
[7:0]
LOSE 7-0 Any change in a LOS Status Register bits will cause the INT pin to go low if corresponding bit
in this register is set to “1”. Register bits default to 00h after power-up or reset.
BIT
NAME
Description
[7:0]
DFME 7-0
Enables interrupts for failures detected by the DFM. Any change in a DFM Status Register bit
will cause an interrupt if the corresponding bit is set to “1” in this register. Register bits
default to 00h after power-up or reset.
BIT
NAME
Description
[7:0]
LOSI 7-0
Bit n of this register is set to “1” to indicate a status change in bit n of the LOS Status Regis-
ter. The bits in this register indicate a change in status since the last cleared LOS interrupt.
Register bits default to 00h after power-up or reset.
BIT
NAME
Description
[7:0]
DFMI 7-0
Bit n of this register is set to “1” to indicate a status change in bit n of the DFM Status Regis-
ter. The bits in this register indicate a change in status since the last cleared DFM interrupt.
Register bits default to 00h after power-up or reset.
BIT
NAME
Description
[7:0]
SRES 7-0 Writing to this register initializes all registers to their default settings. Register bits default to
00h after power-up or reset.
BIT
NAME
Description
[7:4]
RSVD 7-4
RESERVED (These bits must be set to 0.)
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