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參數(shù)資料
| 型號： | CY14E102N-BA20XI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 16 NON-VOLATILE SRAM, 20 ns, PBGA48 |
| 封裝： | 6 X 10 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, FBGA-48 |
| 文件頁數(shù)： | 21/21頁 |
| 文件大小： | 628K |
| 代理商： | CY14E102N-BA20XI |
ADVANCE
CY14E102L, CY14E102N
Document Number: 001-45755 Rev. *A
Page 9 of 21
AC Switching Characteristics
The following table lists the AC switching characteristics.
Parameters
Description
15 ns
20 ns
25 ns
45 ns
Unit
Cypress
Parameters
Alt
Parameters
Min
Max
Min
Max
Min
Max
Min
Max
SRAM Read Cycle
tACE
tACS
Chip Enable Access Time
15
20
25
45
ns
tRC
tRC
Read Cycle Time
15
20
25
45
ns
tAA
tAA
Address Access Time
15
20
25
45
ns
tDOE
tOE
Output Enable to Data Valid
10
12
20
ns
tOHA
tOH
Output Hold After Address
Change
333
3
ns
tLZCE
tLZ
Chip Enable to Output Active
3
ns
tHZCE
tHZ
Chip Disable to Output Inactive
7
8
10
15
ns
tLZOE
tOLZ
Output Enable to Output Active
0
ns
tHZOE
tOHZ
Output Disable to Output
Inactive
7
8
10
15
ns
tPU
tPA
Chip Enable to Power Active
0
ns
tPD
tPS
Chip Disable to Power Standby
15
20
25
45
ns
tDBE
-
Byte Enable to Data Valid
10
12
20
ns
tLZBE
-
Byte Enable to Output Active
0
ns
tHZBE
-
Byte Disable to Output Inactive
7
8
10
15
ns
SRAM Write Cycle
tWC
Write Cycle Time
15
20
25
45
ns
tPWE
tWP
Write Pulse Width
10152030
ns
tSCE
tCW
Chip Enable To End of Write
15152030
ns
tSD
tDW
Data Setup to End of Write
5
8
10
15
ns
tHD
tDH
Data Hold After End of Write
0
ns
tAW
Address Setup to End of Write
10
15
20
30
ns
tSA
tAS
Address Setup to Start of Write
0
ns
tHA
tWR
Address Hold After End of Write
0
ns
tHZWE
tWZ
Write Enable to Output Disable
7
8
10
15
ns
tLZWE
tOW
Output Active after End of Write
3
ns
tBW
-
Byte Enable to End of Write
15152030
ns
Notes
12. WE must be HIGH during SRAM read cycles.
13. Device is continuously selected with CE and OE both LOW.
14. Measured ±200 mV from steady state output voltage.
15. If WE is LOW when CE goes LOW, the output goes into high impedance state.
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