參數(shù)資料
型號(hào)： CY7C1472BV25-250BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 4M X 18 ZBT SRAM, 3 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
文件頁數(shù)： 14/29頁
文件大小： 884K
代理商： CY7C1472BV25-250BZXI
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D
Page 21 of 29
Switching Characteristics
Over the Operating Range. Timing reference is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and
Waveforms” on page 20 unless otherwise noted.
Parameter
Description
–250
–200
–167
Unit
Min
Max
Min
Max
Min
Max
tPower
VCC (typical) to the First Access Read or Write
1
ms
Clock
tCYC
Clock Cycle Time
4.0
5.0
6.0
ns
FMAX
Maximum Operating Frequency
250
200
167
MHz
tCH
Clock HIGH
2.0
2.2
ns
tCL
Clock LOW
2.0
2.2
ns
Output Times
tCO
Data Output Valid After CLK Rise
3.0
3.4
ns
tOEV
OE LOW to Output Valid
3.0
3.4
ns
tDOH
Data Output Hold After CLK Rise
1.3
1.5
ns
tCHZ
Clock to High-Z[16, 17, 18]
3.0
3.4
ns
tCLZ
Clock to Low-Z[16, 17, 18]
1.3
1.5
ns
tEOHZ
OE HIGH to Output High-Z[16, 17, 18]
3.0
3.4
ns
tEOLZ
OE LOW to Output Low-Z[16, 17, 18]
0
ns
Setup Times
tAS
Address Setup Before CLK Rise
1.4
1.5
ns
tDS
Data Input Setup Before CLK Rise
1.4
1.5
ns
tCENS
CEN Setup Before CLK Rise
1.4
1.5
ns
tWES
WE, BWx Setup Before CLK Rise
1.4
1.5
ns
tALS
ADV/LD Setup Before CLK Rise
1.4
1.5
ns
tCES
Chip Select Setup
1.4
1.5
ns
Hold Times
tAH
Address Hold After CLK Rise
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.4
0.5
ns
tCENH
CEN Hold After CLK Rise
0.4
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.4
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.4
0.5
ns
Notes
15. This part has a voltage regulator internally; tpower is the time power is supplied above VDD minimum initially, before a read or write operation can be initiated.
16. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of “AC Test Loads and Waveforms” on page 20. Transition is measured ±200 mV from
steady-state voltage.
17. At any supplied voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
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