參數(shù)資料
型號: CY7C1472BV25-250BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 4M X 18 ZBT SRAM, 3 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
文件頁數(shù): 16/29頁
文件大小: 884K
代理商: CY7C1472BV25-250BZXI
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D
Page 23 of 29
Figure 7 shows NOP, STALL and DESELECT Cycles waveform.
Figure 7. NOP, STALL and DESELECT Cycles
Figure 8 shows ZZ Mode timing waveform.
Figure 8. ZZ Mode Timing
Switching Waveforms (continued)
READ
Q(A3)
456
789
10
CLK
CE
WE
CEN
BWx
ADV/LD
ADDRESS
A3
A4
A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
123
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
tCHZ
A2
D(A1)
Q(A2)
Q(A3)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
A LL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
23. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.
24. IOs are in High-Z when exiting ZZ sleep mode.
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