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參數(shù)資料
| 型號： | CY7C1472BV25-250BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 4M X 18 ZBT SRAM, 3 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 |
| 文件頁數(shù)： | 29/29頁 |
| 文件大?。?/td> | 884K |
| 代理商： | CY7C1472BV25-250BZXI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁當前第29頁
CY7C1470BV25
CY7C1472BV25, CY7C1474BV25
Document #: 001-15032 Rev. *D
Page 9 of 29
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25,
DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474BV25) (or a subset for Byte Write operations, see
“Partial Write Cycle Description” on page 11 for details) inputs is
latched into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d for CY7C1470BV25, BWa,b for CY7C1472BV25, and
BWa,b,c,d,e,f,g,h
for
CY7C1474BV25)
signals.
The
CY7C1470BV25,
CY7C1472BV25,
and
CY7C1474BV25
provides Byte Write capability that is described in “Partial Write
Cycle Description” on page 11. Asserting the WE input with the
selected BW input selectively writes to only the desired bytes.
Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self-timed write mechanism has been
provided to simplify the write operations. Byte Write capability
has been included to greatly simplify read, modify, or write
sequences, which can be reduced to simple Byte Write opera-
tions.
Because
the
CY7C1470BV25,
CY7C1472BV25,
and
CY7C1474BV25 are common IO devices, data must not be
driven into the device while the outputs are active. OE can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1470BV25, DQa,b/DQPa,b for
CY7C1472BV25,
and
DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474BV25) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1470BV25,
DQa,b/DQPa,b for CY7C1472BV25, and
DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1474BV25)
are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in “Single Write Accesses”
on page 8. When ADV/LD is driven HIGH on the subsequent
clock rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs
are ignored and the burst counter is incremented. The correct
BW (BWa,b,c,d for CY7C1470BV25, BWa,b for CY7C1472BV25,
and BWa,b,c,d,e,f,g,h for CY7C1474BV25) inputs must be driven
in each cycle of the burst write to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Table 2. Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Table 3. Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ
> V
DD 0.2V
120
mA
tZZS
Device operation to ZZ
ZZ
> V
DD 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ
< 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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| CY7C1472BV33-167AXI | 功能描述:靜態(tài)隨機存取存儲器 72MB (4Mx18) 3.3v 167MHz 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1472BV33-167BZC | 功能描述:靜態(tài)隨機存取存儲器 4Mx18,3.3V NoBL PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1472BV33-167BZCT | 功能描述:靜態(tài)隨機存取存儲器 4Mx18,3.3V NoBL PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1472BV33-167ZXI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1472BV33-200AXC | 功能描述:靜態(tài)隨機存取存儲器 4Mx18,3.3V NoBL PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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