參數(shù)資料
型號: DAC1008D750HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
封裝: DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 31/99頁
文件大小: 547K
代理商: DAC1008D750HN
DAC1008D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 5 January 2011
31 of 99
NXP Semiconductors
DAC1008D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
Table 13.
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see
Table 28
“DAC_A_CFG_2 register (address 0Ah) bit description”
) and to DAC_B_GAIN_FINE[5:0]
(register 0Dh; see
Table 31 “DAC_B_CFG_2 register (address 0Dh) bit description”
)
define the fine variation of the full-scale current (see
Table 14
).
Table 14.
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0]
Decimal
32
...
0
...
31
The coding of the fine gain adjustment is two’s complement.
10.10 Digital offset correction
When the DAC1008D750 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common-mode level at the output of the DAC.
It adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (register 09h; see
Table 27
“DAC_A_CFG_1 register (address 09h) bit description”
and register 0Bh; see
Table 29
“DAC_A_CFG_3 register (address 0Bh) bit description”
) and to “DAC_B_OFFSET[11:0]”
I
O(fs)
coarse adjustment
I
O(fs)
(mA)
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1.6
3.0
4.4
5.8
7.2
8.6
10.0
11.4
12.8
14.2
15.6
17.0
18.5
20.0
21.0
22.0
I
O(fs)
fine adjustment
Delta I
O(fs)
Two’s complement
10 0000
...
00 0000
...
01 1111
10 %
...
0
...
+10 %
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