參數(shù)資料
型號: DAC1008D750HN
廠商: NXP Semiconductors N.V.
元件分類: 外設及接口
英文描述: Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
封裝: DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 63/99頁
文件大?。?/td> 547K
代理商: DAC1008D750HN
DAC1008D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 5 January 2011
63 of 99
NXP Semiconductors
DAC1008D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
Table 89.
Bit
7 to 4
3 to 0
MAN_ALIGN_LN_2_3 register (address 0Ah) bit description
Symbol
MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN2[3:0]
Access
R/W
R/W
Value
0h
0h
Description
indicates alignment data-delay for lane 3 [1..15]
indicates alignment data-delay for lane 2 [1..15]
Table 90.
Default settings are shown highlighted.
Bit
Symbol
7 to 6
SEL_KOUT_ UNEXP_LN23[1:0]
FA_ERR_HANDLING register (address 0Bh) bit description
Access
R/W
Value
Description
lane 2/lane 3 unexpected /K/ error handling
unexpected /K/ in lane 2 or lane 3
error_handling
unexpected /K/ in lane 2 and lane 3 error_handling
unexpected /K/ in lane 2 error_handling
unexpected /K/ in lane 3 error_handling
lane 0/lane 1 unexpected /K/ error handling
unexpected /K/ in lane 0 or lane 1
error_handling
unexpected /K/ in lane 0 and lane 1 error_handling
unexpected /K/ in lane 0 error_handling
unexpected /K/ in lane 1 error_handling
lane 2/lane 3 nit-error handling
nit-errors in lane 2 or lane 3
error_handling
not-in-table errors lane 2 and lane 3
error_handling
not-in-table errors in lane 2 error_handling
not-in-table errors in lane 3 error_handling
lane 0/lane 1 nit-error handling
nit-errors in lane 0 or lane 1
error_handling
not-in-table errors lane 0 and lane 1
error_handling
not-in-table errors in lane 0 error_handling
not-in-table errors in lane 1 error_handling
00
01
10
11
5 to 4
SEL_KOUT_ UNEXP_LN10[1:0]
R/W
00
01
10
11
3 to 2
SEL_NIT_ERR_ LN23[1:0]
R/W
00
01
10
11
1 to 0
SEL_NIT_ERR_ LN10[1:0]
R/W
00
01
10
11
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