參數(shù)資料
型號: DAC1008D750HN
廠商: NXP Semiconductors N.V.
元件分類: 外設及接口
英文描述: Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
封裝: DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 55/99頁
文件大?。?/td> 547K
代理商: DAC1008D750HN
DAC1008D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 5 January 2011
55 of 99
NXP Semiconductors
DAC1008D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
Table 70.
Default settings are shown highlighted.
Bit
Symbol
7
DAC
TYPE_ID register (address 1Bh) bit description
Access
R
Value
Description
part type
ADC
DAC
input format
CMOS
LVDS
JESD204A
reserved
converter structure
single
dual
digital processing
none
upsampling filters
single sideband modulator
upsampling filters + single sideband
modulator
resolution
0
1
6 to 5
FRONTEND [1:0]
R
00
01
10
11
4
DUAL
R
0
1
3 to 2
DSP
R
00
01
10
11
1 to 0
BIT_RES[1:0]
R
00
01
10
11
16 bits
14 bits
12 bits
10 bits
Table 71.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
DAC_VERSION_ID[7:0]
DAC_VERSION register (address 1Ch) bit description
Access
R
Value
01h
Description
dual DAC core version
Table 72.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
DIG_VERSION_ID[7:0]
DIG_VERSION register (address 1Dh) bit description
Access
R
Value
02h
Description
digital version
Table 73.
Default settings are shown highlighted.
Bit
Symbol
7 to 0
JRX_ANA_VERSION_ID[7:0]
JRX_ANA_VERSION register (address 1Eh) bit description
Access
R
Value
02h
Description
analog deserializer version
Table 74.
Default settings are shown highlighted.
Bit
Symbol
2 to 0
PAGE[2:0]
PAGE_ADDRESS register (address 1Fh) bit description
Access
R/W
Value
0h
Description
page address
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