參數(shù)資料
型號： DAC1008D750HN
廠商： NXP Semiconductors N.V.
元件分類： 外設及接口
英文描述： Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
封裝： DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D750HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù)： 62/99頁
文件大小： 547K
代理商： DAC1008D750HN
DAC1008D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 5 January 2011
62 of 99
NXP Semiconductors
DAC1008D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
Table 86.
Bit
7
ILA_CNTRL register (address 07h) bit description
Symbol
SEL_421_211
Access
R/W
Value
Description
inter-lane alignment mode
inter-lane alignment based on lane 3 : lane 2
and/or lane 1 : lane 0
inter-lane alignment based on ln3 : ln0
inter-lane alignment trigger mode
inter-lane alignment is done after receiving
1 /A/-symbol
inter-lane alignment is done after receiving
2 /A/-symbols
inter-lane alignment is done after receiving
3 /A/-symbols
inter-lane alignment is done after receiving
4 /A/-symbols
inter-lane alignment start mode
inter-lane alignment may start only if all (4 or 2)
lanes are locked
inter-lane alignment may start if one of the (4 or 2)
lanes are locked
inter-lane alignment may start if lane 0 is locked
inter-lane alignment may start if lane 1 is locked
inter-lane alignment may start if lane 2 is locked
inter-lane alignment may start if lane 3 is locked
inter-lane alignment enable
inter-lane alignment synchronization disabled
inter-lane alignment synchronization enabled
data descrambling
disabled
enabled
0
1
6 to 5
SEL_ILA[1:0]
R/W
00
01
10
11
4 to 2
SEL_LOCK[2:0]
R/W
000
001
010
011
100
101
1
SUP_LANE_SYN
R/W
0
1
0
EN_SCR
R/W
0
1
Table 87.
Bit
1
FORCE_ALIGN register (address 08h) bit description
Symbol
DYN_ALIGN_ENA
Access
R/W
Value
Description
dynamic re-alignment mode
no dynamic re-alignment
dynamic re-alignment (and monitoring) enabled
lane alignment mode
automatic lane alignment based on
/A/ symbols
manual lane alignment based on man_align_lnx
0
1
0
FORCE_ALIGN
R/W
0
1
Table 88.
Bit
7 to 4
3 to 0
MAN_ALIGN_LN_0_1 register (address 09h) bit description
Symbol
MAN_ALIGN_LN1[3:0]
MAN_ALIGN_LN0[3:0]
Access
R/W
R/W
Value
0h
0h
Description
indicates alignment data-delay for lane 1 [1..15]
indicates alignment data-delay for lane 0 [1..15]
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相關代理商/技術參數(shù)
參數(shù)描述
DAC1008D750HN/C1,5 功能描述:數(shù)模轉換器- DAC DL 10BIT DAC 750MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 轉換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC1008LCN 制造商:Texas Instruments 功能描述:
DAC1008LCN/A+ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter
DAC100ACQ3 制造商:Analog Devices 功能描述:
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