- 您現在的位置：買賣IC網 > PDF目錄376597 > DDC112 Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER PDF資料下載
參數資料
| 型號： | DDC112 |
| 英文描述： | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙路電流輸入20位模擬數字轉換器 |
| 文件頁數： | 11/24頁 |
| 文件大?。?/td> | 210K |
| 代理商： | DDC112 |
DDC112
11
TEST and CONV work together to implement this feature.
The test mode is entered when TEST is HIGH prior to a
CONV edge. At that point, a CONV edge triggers the
grounding of the analog inputs and the switching of 13pC
packets of charge onto the integration capacitors. If TEST is
kept HIGH through at least two conversions (i.e., a rise and
fall of CONV), all four integrators will be charged with a
13pC packet. At the end of each conversion, the voltage at
the output of the integrators is digitized as discussed in the
“Continuous Mode” and “Non-Continuous Mode” section
of this data sheet. The test mode is exited when TEST is
LOW and a CONV edge occurs.
Once the test mode is entered as described above, TEST can
cycle as many times as desired. When this is done, additional
13pC packets are added on the rising edge of TEST to the
existing charge on the integrator capacitors. Multiple charge
packets can be added in this way as long as the TEST pin is
not LOW when CONV toggles.
DIGITAL ISSUES
The digital interface of the DDC112 provides the digital
results via a synchronous serial interface consisting of a data
clock (DCLK), a transmit enable pin (DXMIT), a valid data
pin (DVALID), a serial data output pin (DOUT), and a serial
data input pin (DIN). The DDC112 contains only one A/D
converter, so the conversion process is interleaved between
the two inputs (see Figure 2). The integration and conversion
process is fundamentally independent of the data retrieval
process. Consequently, the CLK frequency and DCLK fre-
quencies need not be the same. DIN is used when multiple
converters are cascaded. Cascading or “daisy chaining”
greatly simplifies the interconnection and routing of the
digital outputs in cases where a large number of converters
are needed. Refer to “Cascading Multiple Converters” section
of this data sheet for more detail.
The conversion rate of the DDC112 is set by a combination
of the integration time (determined by the user) and the speed
of the A/D conversion process. The A/D conversion time is
primarily a function of the system clock (CLK) speed. One
A/D conversion cycle encompasses the conversion of two
signals (one from each input of the DDC112) and reset time
for each of the integrators involved in the two conversions. In
most situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC112 will
operate in the continuous mode. When the DDC112 is in the
continuous mode, the sensor output is continuously integrated
by one of the two sides of each input.
In the event that the A/D conversion takes longer than the
integration time, the DDC112 will switch into a non-con-
tinuous mode. In non-continuous mode, the A/D converter is
not able to keep pace with the speed of the integration
process. Consequently, the integration process is periodi-
cally halted until the digitizing process catches up. These
two basic modes of operation for the DDC112—continuous
and non-continuous modes—are described below.
Continuous and Non-Continuous
Operational Modes
The state diagram of the DDC112 is shown in Figure 9. In
all, there are 8 states. Table IV provides a brief explanation
of each of the states.
STATE
MODE
DESCRIPTION
1
Ncont
Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.
2
Ncont
Prepare side A for integration.
3
Cont
Integrate on side A.
4
Cont
Integrate on side B; m/r/az on side A.
5
Cont
Integrate on side A; m/r/az on side B.
6
Cont
Integrate on side B.
7
Ncont
Prepare side B for integration.
8
Ncont
Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.
TABLE IV. State Descriptions.
Int A/Meas B
Cont
5
CONV mbsy
CONV mbsy
CONV mbsy
CONV mbsy
CONV mbsy
CONV mbsy
CONV
CONV
Int B/Meas A
Cont
4
Ncont
1
Ncont
2
Int A
Cont
3
Ncont
8
Ncont
7
Int B
Cont
6
CONV
CONV
mbsy
mbsy
FIGURE 9. State Diagram.
Four signals are used to control progression around the state
diagram: CONV and mbsy and their complements. The state
machine uses the level as opposed to the edges of CONV to
control the progression. mbsy is an internally generated
signal not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in progress.
相關PDF資料 |
PDF描述 |
|---|---|
| DDC112U | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC112UK | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC118 | Octal Current Input 20-Bit Analog-To-Digital Converter |
| DDC118IRTCR | Octal Current Input 20-Bit Analog-To-Digital Converter |
| DDC118IRTCT | Octal Current Input 20-Bit Analog-To-Digital Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DDC1128ZKLT | 功能描述:20 Bit Analog to Digital Converter 128 Input 1 Sigma-Delta 192-NFBGA (9x9) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數:20 采樣率（每秒）:6.25k 輸入數:128 輸入類型:單端 數據接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉換器數:1 架構:三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數字:2.7 V ~ 3.6 V 特性:同步采樣 工作溫度:0°C ~ 70°C 封裝/外殼:192-LFBGA 供應商器件封裝:192-NFBGA（9x9） 標準包裝:1 |
| DDC112U | 功能描述:模數轉換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL 3KHZ SOIC28 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112; Resolution (Bits):20bit; Sampling Rate:3kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:14.8mA; Digital IC Case Style:SOIC; No. of Pins:28; ;RoHS Compliant: Yes |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112 |
| DDC112U | 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL |
發(fā)布緊急采購，3分鐘左右您將得到回復。