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參數(shù)資料
| 型號： | DDC112 |
| 英文描述： | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙路電流輸入20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 210K |
| 代理商： | DDC112 |
12
DDC112
TABLE V. Timing Specifications Generalized in CLK Periods.
SYMBOL
DESCRIPTION
VALUE (CLK periods)
t
6
t
7
Cont mode m/r/az cycle
Cont mode data ready
4794
4212
4212
±
3
4212
±
3
4548
9108
≥
240
(t
INT
> 4794)
(t
INT
= 4794)
t
8
t
9
t
10
t
11
1st ncont mode data ready
2nd ncont mode data ready
Ncont mode m/r/az cycle
Prepare side for integration
4
3
2
1
5
4
Integrate B
Integrate A
Integrate A
Integrate B
m/r/az A
t
6
m/r/az B
m/r/az A
CONV
State
mbsy
m/r/az
Status
Integration
Status
DVALID
t
7
t = 0
Power-Up
Side A
Data
Side B
Data
Side A
Data
FIGURE 10. Continuous Mode Timing (CONV HIGH at power-up).
SYMBOL
DESCRIPTION
VALUE (CLK = 10MHz)
VALUE (CLK = 15MHz)
t
6
t
7
Cont mode m/r/az cycle
Cont mode data ready
479.4
μ
s
421.2
μ
s
421.2
±
0.3
μ
s
316.4
μ
s
280.5
μ
s
280.5
±
0.2
μ
s
(T
INT
> 479.4
μ
s)
(T
INT
= 479.4
μ
s)
(T
INT
> 316.4
μ
s)
(T
INT
= 316.4
μ
s)
During the cont mode, mbsy is not active when CONV
toggles. The non-integrating side is always ready to begin
integrating when the other side finishes its integration.
Consequently, keeping track of the current status of CONV
is all that is needed to know the current state. Cont mode
operation corresponds to states 3-6. Two of the states, 3 and
6, only perform an integration (no m/r/az cycle).
mbsy becomes important when operating in the ncont mode;
states 1, 2, 7, and 8. Whenever CONV is toggled while mbsy
is active, the DDC112 will enter or remain in either ncont
state 1 (or 8). After mbsy goes inactive, state 2 (or 7) is
entered. This state prepares the appropriate side for integra-
tion. As mentioned above, in the ncont states, the inputs to
the DDC112 are grounded.
One interesting observation from the state diagram is that
the integrations always alternate between sides A and B.
This relationship holds for any CONV pattern and is inde-
pendent of the mode. States 2 and 7 insure this relationship
during the ncont mode.
When power is first applied to the DDC112, the beginning
state is either 1 or 8, depending on the initial level of CONV.
For CONV held HIGH at power-up, the beginning state is 1.
Conversely, for CONV held LOW at power-up, the begin-
ning state is 8. In general, there is a symmetry in the state
diagram between states 1-8, 2-7, 3-6 and 4-5. Inverting
CONV results in the states progressing through their sym-
metrical match.
TIMING EXAMPLES
Cont Mode
A few timing diagrams will now be discussed to help
illustrate the operation of the state machine. These are
shown in Figures 10 through 19. Table V gives generalized
timing specifications in units of CLK periods. Values in
μ
s
for Table V can be easily found for a given CLK. For
example, if CLK = 10MHz, then a CLK period = 0.1
μ
s. t
6
in Table V would then be 479.4
μ
s.
Figure 10 shows a few integration cycles beginning with
initial power-up for a cont mode example. The top signal is
CONV and is supplied by the user. The next line indicates
the current state in the state diagram. The following two
traces show when integrations and measurement cycles are
underway. The internal signal mbsy is shown next. Finally,
DVALID is given. As described in the data sheet, DVALID
goes active LOW when data is ready to be retrieved from the
DDC112. It stays LOW until DXMIT is taken LOW by the
user. In Figure 10 and the following timing diagrams, it is
assumed that DXMIT it taken LOW soon after DVALID
goes LOW. The text below the DVALID pulse indicates the
side of the data and arrows help match the data to the
corresponding integration. The signals shown in Figures 10
through 19 are drawn at approximately the same scale.
In Figure 10, the first state is ncont state 1. The DDC112
always powers up in the ncont mode. In this case, the first
state is 1 because CONV is initially HIGH. After the first
two states, cont mode operation is reached and the states
begin toggling between 4 and 5. From now on, the input is
being continuously integrated, either by side A or side B.
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相關(guān)代理商/技術(shù)參數(shù) |
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| DDC1128ZKLT | 功能描述:20 Bit Analog to Digital Converter 128 Input 1 Sigma-Delta 192-NFBGA (9x9) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):20 采樣率（每秒）:6.25k 輸入數(shù):128 輸入類型:單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 3.6 V 特性:同步采樣 工作溫度:0°C ~ 70°C 封裝/外殼:192-LFBGA 供應(yīng)商器件封裝:192-NFBGA（9x9） 標(biāo)準(zhǔn)包裝:1 |
| DDC112U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL 3KHZ SOIC28 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112; Resolution (Bits):20bit; Sampling Rate:3kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:14.8mA; Digital IC Case Style:SOIC; No. of Pins:28; ;RoHS Compliant: Yes |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112 |
| DDC112U | 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL |
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