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參數(shù)資料
| 型號： | DDC112 |
| 英文描述： | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙路電流輸入20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 210K |
| 代理商： | DDC112 |
14
DDC112
FIGURE 13. Non-Continuous Mode Timing.
Ncont Mode
Figure 13 illustrates operation in the ncont mode. The
integrations come in pairs (i.e., sides A/B or sides B/A)
followed by a time during which no integrations occur.
During that time, the previous integrations are being mea-
sured, reset and auto-zeroed. Before the DDC112 can ad-
vance to states 3 or 6, both sides A and B must be finished
with the m/r/az cycle which takes time t
10
. When the m/r/az
cycles are completed, time t
11
is needed to prepare the next
side for integration. This time is required for the ncont
mode because the m/r/az cycle of the ncont mode is slightly
different from that of the cont mode. After the first integra-
tion ends, DVALID goes LOW in time t
8
. This is the same
time as in the cont mode. The second data will be ready in
time t
9
after the first data is ready. One result of the naming
convention used in this application bulletin is that when the
DDC112 is operating in the “ncont mode”, it passes through
both “ncont mode states” and “cont mode states”. For
example, in Figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1,
2, 3, 4...where 3 and 4 are cont mode states. “Ncont mode”
by definition means that for some portion of the time,
neither side A nor B is integrating. States that perform an
integration are labeled “cont mode states” while those that
do not are called “ncont mode states”. Since integrations are
performed in the ncont mode, just not continuously, some
cont mode states must be used in a ncont mode state pattern.
SYMBOL
DESCRIPTION
VALUE (CLK = 10MHz)
VALUE (CLK = 15MHz)
t
8
t
9
t
10
t
11
1st ncont mode data ready
2nd ncont mode data ready
Ncont mode m/r/az cycle
Prepare side for integration
421.2
±
0.3
μ
s
4548.0
μ
s
910.8
μ
s
≥
24.0
μ
s
280.5
±
0.2
μ
s
3028.9
μ
s
601.1
μ
s
≥
24.0
μ
s
2
3
1
3
4
4
1
2
Int B
Int A
Int B
Int A
m/r/az B
m/r/az A
m/r/az A
m/r/az B
CONV
State
mbsy
m/r/az
Status
Integration
Status
DVALID
t
10
t
9
t
11
t
8
Side A
Data
Side B
Data
Side A
Data
Side B
Data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDC1128ZKLT | 功能描述:20 Bit Analog to Digital Converter 128 Input 1 Sigma-Delta 192-NFBGA (9x9) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):20 采樣率（每秒）:6.25k 輸入數(shù):128 輸入類型:單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 3.6 V 特性:同步采樣 工作溫度:0°C ~ 70°C 封裝/外殼:192-LFBGA 供應(yīng)商器件封裝:192-NFBGA（9x9） 標準包裝:1 |
| DDC112U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL 3KHZ SOIC28 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112; Resolution (Bits):20bit; Sampling Rate:3kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:14.8mA; Digital IC Case Style:SOIC; No. of Pins:28; ;RoHS Compliant: Yes |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112 |
| DDC112U | 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL |
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