參數(shù)資料
型號(hào): DDC112
英文描述: Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述: 雙路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 19/24頁(yè)
文件大?。?/td> 210K
代理商: DDC112
DDC112
19
FIGURE 20. Daisy-Chained DDC112’s.
IN1
IN2
DCLK
DXMIT
DIN
DVALID
DOUT
DDC112
“F” “E”
Sensor “F”
Sensor “E”
IN1
IN2
DCLK
DXMIT
DIN
DVALID
DOUT
DDC112
“D” “C”
Sensor “D”
Sensor “C”
IN1
IN2
DCLK
DXMIT
DIN
DVALID
DOUT
Data Retrieval
Outputs
DDC112
“B” “A”
Sensor “B”
Sensor “A”
R
P
R
P
R
P
Data Retrievel
Inputs
40 Bits
40 Bits
40 Bits
FIGURE 21. DDC112 in Parallel Operation.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
18
t
19
t
20
t
21
t
22
t
23
Propagation Delay from Rising Edge of CLK to DVALID LOW
Propagation Delay from DXMIT LOW to DVALID HIGH
Setup Time from DCLK LOW TO DXMIT LOW
Propagation Delay from DXMIT LOW to Valid DOUT
Hold Time that DOUT is Valid After Falling Edge of DCLK
Propagation Delay from DXMIT HIGH to DOUT Disabled
Propagaton Delay from Falling Edge of DCLK to Valid DOUT
Propagation Delay from Falling Edge of DCLK to Valid DOUT
30
30
ns
ns
ns
ns
ns
ns
ns
ns
20
30
5
30
t
22A(1)
t
22B(2)
25
30
NOTES: (1) Applies to DDC112UK only, with a maximum load of one DDC112UK DIN (4pF typical) with an additional load of (5pF
100k
). (2)
Applies to
DDC112U only, with a maximum load of one DDC112U DIN (4pF typical) with an additional load of (5pF
100k
).
FIGURE 22. Digital Interface Timing Diagram for Data Retrieval From a Single DDC112.
TABLE IX. Timing for the DDC112 Data Retrieval.
DIN
DIN
DIN
DOUT
DXMIT
DDC112
Data Output
DDC112
DDC112
Enable
DOUT
DXMIT
DOUT
DXMIT
t
18
t
19
t
20
t
21
t
22
t
23
IBit 1
MSB
Output Enabled
IBit 20
LSB
IBit 1
MSB
IBit 20
LSB
Output Disabled
Output Disabled
CLK
DVALID
DXMIT
DCLK
(1)
DOUT
NOTE: (1) Disable DCLK (preferably hold LOW) when DXMIT is HIGH.
相關(guān)PDF資料
PDF描述
DDC112U Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
DDC112UK Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
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相關(guān)代理商/技術(shù)參數(shù)
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