DDC112
3
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
IN1
Input 1: analog input for Integrators 1A and 1B. The
integrator that is active is set by the CONV input.
2
AGND
Analog Ground.
3
CAP1B
External Capacitor for Integrator 1B.
4
CAP1B
External Capacitor for Integrator 1B.
5
CAP1A
External Capacitor for Integrator 1A.
6
CAP1A
External Capacitor for Integrator 1A.
7
AV
DD
TEST
Analog Supply, +5V nominal.
8
Test Control Input. When HIGH, a test charge is
applied to the A or B integrators on the next CONV
transition.
9
CONV
Controls which side of the integrator is connected to
input. In continuous mode; CONV HIGH
→
side A is
integrating, CONV LOW
→
side B is integrating.
CONV must be synchronized with CLK (see text).
10
CLK
System Clock Input, 10MHz nominal.
11
DCLK
Serial Data Clock Input. This input operates the
serial I/O shift register.
12
DXMIT
Serial Data Transmit Enable Input. When LOW, this
input enables the internal serial shift register.
13
DIN
Serial Digital Input. Used to cascade multiple
DDC112s.
14
DV
DD
DGND
Digital Supply, +5V nominal.
15
Digital Ground.
16
DOUT
Serial Data Output, Hi-Z when DXMIT is HIGH.
17
DVALID
Data Valid Output. A LOW value indicates valid data
is available in the serial I/O register.
18
RANGE0
Range Control Input 0 (least significant bit).
19
RANGE1
Range Control Input 1.
20
RANGE2
Range Control Input 2 (most significant bit).
21
AGND
Analog Ground.
22
V
REF
CAP2A
External Reference Input, +4.096V nominal.
23
External Capacitor for Integrator 2A.
24
CAP2A
External Capacitor for Integrator 2A.
25
CAP2B
External Capacitor for Integrator 2B.
26
CAP2B
External Capacitor for Integrator 2B.
27
AGND
Analog Ground.
28
IN2
Input 2: analog input for Integrators 2A and 2B. The
integrator that is active is set by the CONV input.
The information provided herein is believed to be reliable; however, BURR-BROWN
assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be
entirely at the user’s own risk. Prices and specifications are subject to change without
notice. No patent rights or licenses to any of the circuits described herein are implied or
granted to any third party. BURR-BROWN does not authorize or warrant any BURR-
BROWN product for use in life support devices and/or systems.
AV
DD
to DV
....................................................................... –0.3V to +6V
AV
DD
to AGND ..................................................................... –0.3V to +6V
DV
to DGND ..................................................................... –0.3V to +6V
AGND to DGND ...............................................................................
±
0.3V
V
Voltage to AGND ............................................ –0.3V to AV
DD
+0.3V
Digital Input Voltage to DGND ................................ –0.3V to DV
DD
+0.3V
Digital Output Voltage to DGND ............................. –0.3V to DV
+0.3V
Package Power Dissipation............................................. (T
– T
)/
θ
JA
Maximum Junction Temperature (T
) ...................................... +150
°
C
Thermal Resistance,
θ
............................................................. 150
°
C/W
Lead Temperature (soldering, 10s)............................................... +300
°
C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maxi-
mum conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
PIN CONFIGURATION
Top View
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IN2
AGND
CAP2B
CAP2B
CAP2A
CAP2A
V
REF
AGND
RANGE2 (MSB)
RANGE1
RANGE0 (LSB)
DVALID
DOUT
DGND
IN1
AGND
CAP1B
CAP1B
CAP1A
CAP1A
AV
DD
TEST
CONV
CLK
DCLK
DXMIT
DIN
DV
DD
DDC112
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY ERROR
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
DRAWING
NUMBER
ORDERING
NUMBER
(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DDC112U
"
DDC112UK
"
±
0.025% Reading
±
1.0ppm% FSR
"
±
0.025% Reading
±
1.0ppm% FSR
"
–40
°
C to +85
°
C
"
0
°
C to +70
°
C
"
SO-28
"
SO-28
"
217
"
217
"
DDC112U
DDC112U/1K
DDC112UK
DDC112UK/1K
Rails
Tape and Reel
Rails
Tape and Reel
NOTES:
(1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DDC112U/1K” will get a single 1000-piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes
could cause the device not to meet its published specifications.