參數(shù)資料
型號: DDC112
英文描述: Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述: 雙路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 24/24頁
文件大?。?/td> 210K
代理商: DDC112
24
DDC112
FIGURE 30. Recommended Shield for DDC112 Layout
Design.
FIGURE 29. Power Supply Connection Options.
DDC112
0.1
μ
F
< 10
10
μ
F
V
S
+
One +5V Supply
AV
DD
DV
DD
AV
DD
DV
DD
DDC112
0.1
μ
F
0.1
μ
F
0.1
μ
F
10
μ
F
V
S
+
Separate +5V Supplies
10
μ
F
V
DD
+
7
14
7
14
LAYOUT
Power Supplies and Grounding
Both AV
DD
and DV
DD
should be as quiet as possible. It is
particularly important to eliminate noise from AV
DD
that is
non-synchronous with the DDC112 operation. Figure 29
illustrates two acceptable ways to supply power to the
DDC112. The first case shows two separate +5V supplies
for AV
DD
and DV
DD
. In this case, each +5V supply of the
DDC112 should be bypassed with 10
μ
F solid tantalum
capacitors and 0.1
μ
F ceramic capacitors. The second case
shows the DV
DD
power supply derived from the AV
DD
supply with a < 10
isolation resistor. In both cases, the
0.1
μ
F capacitors should be placed as close to the DDC112
package as possible.
Shielding Analog Signal Paths
As with any precision circuit, careful printed circuit layout
will ensure the best performance. It is essential to make
short, direct interconnections and avoid stray wiring capaci-
tance—particularly at the analog input pins. Digital signals
should be kept as far from the analog input signals as
possible on the PC board.
Input shielding practices should be taken into consideration
when designing the circuit layout for the DDC112. The
inputs to the DDC112 are high impedance and extremely
sensitive to extraneous noise. Leakage currents between the
PCB traces can exceed the input bias current of the DDC112
if shielding is not implemented. Figure 30 illustrates an
acceptable approach to this problem. A PC ground plane is
placed around the inputs of the DDC112 (pins 1 and 28).
This shield helps minimize coupled noise into the input pins.
Additionally, the pins that are used for the external integra-
tion capacitors (pins 3, 4, 5, 6, 23, 24, 25 and 26) should be
guarded by a ground plane when the external capacitors are
used.
The approach above reduces leakage affects by surrounding
these sensitive pins with a low impedance analog ground.
Leakage currents from other portions of the circuit will flow
harmlessly to the low impedance analog ground rather than
into the analog input stage of the DDC112.
DDC112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Digital I/O
and
Digital Power
Digital I/O
and
Digital Power
Shield
external
caps when
used
Analog
Ground
Analog
Power
Shield
external
caps when
used
Analog
Ground
Analog
Ground
IN1
IN2
Analog
Ground
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相關(guān)代理商/技術(shù)參數(shù)
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DDC112U 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112
DDC112U 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL