參數(shù)資料
型號(hào)： DDC112
英文描述： Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
中文描述： 雙路電流輸入20位模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 210K
代理商： DDC112
20
DDC112
RETRIEVAL BEFORECONV TOGGLES
(CONTINUOUS MODE)
This is the most straightforward method. Data retrieval
begins soon after DVALID goes LO and finishes before
CONV toggles, see Figure 24. For best performance, data
retrieval must stop t
28
before CONV toggles. This method is
the most appropriate for longer integration times. The maxi-
mum time available for readback is T
INT
– t
27
– t
28
.
For DCLK and CLK = 10MHz, the maximum number of
DDC112s that can be daisy-chained together is:
Where
τ
DCLK
is the period of the data clock. For example, if
TINT = 100
μ
s and DCLK = 10MHz, the maximum number
of DDC112s is:
RETRIEVAL AFTERCONV TOGGLES
(CONTINUOUS MODE)
For shorter integration times, more time is available if data
retrieval begins after CONV toggles and ends before the
new data is ready. Data retrieval must wait t
29
after CONV
toggles before beginning. Figure 25 shows an example of
this. The maximum time available for retrieval is t
27
– t
29
–
t
26
(421.2
μ
s – 10
μ
s –2
μ
s for CLK = 10MHz), regardless of
TINT. The maximum number of DDC112s that can be
daisy-chained together is:
For DCLK = 10MHz, the maximum number of DDC112s is
102.
FIGURE 23. Timing Diagram When Using the DIN Function of the DDC112.
T
s
INT
DCLK
–
.
431 2
40
μ
τ
1000
431 2
ns
40 100
)(
142 2
142
112
μ
μ
=
→
s
s
DDC
s
–
.
(
)
.
409 2
40
τ
.
μ
s
DCLK
t
18
t
14
t
20
t
21
t
22
t
23
t
24
t
25
Output Disabled
Output Enabled
Output Disabled
CLK
DVALID
DXMIT
DCLK
(1)
DIN
Input A
Bit 1
MSB
Input E
Bit 20
LSB
Input F
Bit 1
MSB
Input F
Bit 20
LSB
DOUT
NOTE: (1) Disable DCLK (preferably LOW) when DXMIT is HIGH.
t
26
t
22A,
t
22B
TABLE X. Timing for the DDC112 Data Retrieval Using DIN.
CLK = 10MHz
CLK = 15MHz
SYMBOL
DESCRIPTION
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t
24
t
25
t
26
Set-Up Time From DIN to Rising Edge of DCLK
Hold Time For DIN After Rising Edge of DCLK
Hold Time for DXMIT HIGH Before Falling
Edge of DVALID
10
10
2
5
10
1.33
ns
ns
μ
s
相關(guān)PDF資料
PDF描述
DDC112U Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DDC1128ZKLT 功能描述:20 Bit Analog to Digital Converter 128 Input 1 Sigma-Delta 192-NFBGA (9x9) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):20 采樣率（每秒）:6.25k 輸入數(shù):128 輸入類型:單端 數(shù)據(jù)接口:SPI 配置:ADC 無(wú)線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 3.6 V 特性:同步采樣 工作溫度:0°C ~ 70°C 封裝/外殼:192-LFBGA 供應(yīng)商器件封裝:192-NFBGA（9x9） 標(biāo)準(zhǔn)包裝:1
DDC112U 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
DDC112U 制造商:Texas Instruments 功能描述:20BIT ADC DUAL 3KHZ SOIC28 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112; Resolution (Bits):20bit; Sampling Rate:3kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:14.8mA; Digital IC Case Style:SOIC; No. of Pins:28; ;RoHS Compliant: Yes
DDC112U 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112
DDC112U 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL
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