參數(shù)資料
型號: DS32512N+
廠商: Maxim Integrated Products
文件頁數(shù): 108/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 12P 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
79 of 130
9.6 B3ZS/HDB3 Encoder Registers
ADDRESS
OFFSET
REGISTER
REGISTER DESCRIPTION
30h
B3ZS/HDB3 Transmit Control Register
32h–3Eh
Unused
Register Name:
LINE.TCR
Register Description:
B3ZS/HDB3 Transmit Control Register
Register Address:
n * 80h + 30h
Bit #
15
14
13
12
11
10
9
8
Name
Default
0
Bit #
7
6
5
4
3
2
1
0
Name
TZSD
EXZI
BPVI
TSEI
MEIMS
Default
0
Bit 4: Transmit Zero Suppression Encoding Disable (TZSD)
0 = zero suppression (B3ZS or HDB3) encoding is enabled
1 = zero suppression (B3ZS or HDB3) encoding is disabled, and only AMI encoding is performed
Bit 3: Excessive Zero Insert Enable (EXZI).
See Section 8.2.3.
0 = excessive zero event (EXZ) insertion is disabled
1 = excessive zero event insertion is enabled
Bit 2: Bipolar Violation Insert Enable (BPVI).
See Section 8.2.3.
0 = bipolar violation (BPV) insertion is disabled
1 = bipolar violation insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI).
When LINE.TCR:MEIMS = 0, this bit is used to insert errors of the
type(s) specified by EXZI and BPVI in the transmit data stream. A zero-to-one transition causes a single error to be
inserted. For a second error to be inserted, this bit must be set to 0, and then back to 1. Note: If LINE.TCR:MEIMS
is low, and this bit transitions more than once between error insertion opportunities, only one error is inserted. See
Section 8.7.5.
Bit 0: Manual Error Insert Mode Select (MEIMS).
This bit specifies the source of the error insertion signal for the
transmit encoder/decoder block. Note: If the TMEI pin or TSEI bit is one, changing the state of this bit may cause
an error to be inserted. See Section 8.7.5.
0 = Block-level error insertion using the LINE.TCR:TSEI control bit
1 = Port-level or global-level error insertion as specified by PORT.CR1:MEIMS
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