參數(shù)資料
型號: DS32512N+
廠商: Maxim Integrated Products
文件頁數(shù): 45/130頁
文件大?。?/td> 0K
描述: IC LIU DS3/E3/STS-1 12P 484-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
類型: 線路接口裝置(LIU)
規(guī)程: DS3
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-BGA(23x23)
包裝: 管件
DS32506/DS32508/DS32512
21 of 130
Table 7-6. Parallel Interface Pin Descriptions
NAME
TYPE
FUNCTION
CS
I
Chip Select (Active Low). This pin must be asserted to read or write internal registers. See
Section 8.8.3.
RD/DS
I
Read Enable (Active Low)/Data Strobe (Active Low)
RD: For the Intel-style bus (IFSEL = 1X0), RD is asserted to read internal registers.
DS: For the Motorola-style bus (IFSEL = 1X1), DS is asserted to access internal registers while
the R/W pin specifies whether the access is a read or a write. See Section 8.8.3.
WR/R/W
I
Write Enable (Active Low)/Read/Write Select
WR: For the Intel-style bus (IFSEL = 1X0), WR is asserted to write internal registers.
R/W: For the Motorola-style bus (IFSEL = 1X1), R/W determines the type of bus transaction,
with R/W = 1 indicating a read and R/W = 0 indicating a write. See Section 8.8.3.
ALE
I
Address Latch Enable. This pin controls a latch on the A[10:0] inputs. For a nonmultiplexed
parallel bus, ALE is wired high to make the latch transparent. For a multiplexed parallel bus, the
falling edge of ALE latches the address. See Section 8.8.3.
A[10:1]
I
Address Bus (Excluding LSB). These inputs specify the address of the internal 16-bit register
to be accessed. A10 is not present on the DS32506. See Section 8.8.
A[0] /
BSWAP
I
Address Bus LSB/Byte Swap. See Section 8.8.2.
A[0]: This pin is connected to the lower address bit in 8-bit bus modes (IFSEL = 10X).
0 = Output register bits 7:0 on D[7:0]; D[15:8] high impedance
1 = Output register bits 15:8 on D[7:0]; D[15:8] high impedance
BSWAP: This pin is tied high or low in 16-bit bus modes (IFSEL = 11X).
0 = Output register bits 15:8 on D[15:8] and bits 7:0 on D[7:0]
1 = Output register bits 7:0 on D[15:8] and bits 15:8 on D[7:0]
D[15:0]
I/O
Data Bus. A 8-bit or 16-bit bidirectional data bus. These pins are inputs during writes to internal
registers and outputs during reads. D[15:8] are disabled (high impedance) in 8-bit bus modes
(IFSEL = 10X). D[15:0] are disabled (high impedance) when
CS = 1 or RST = 0. In 16-bit bus
modes (IFSEL = 11X) the upper and lower bytes can be swapped by pulling the BSWAP pin
high. See Section 8.8.
RDY/
ACK
Oz
Ready Handshake (Tri-State)/Acknowledge Handshake (Tri-State, Active Low). Tri-stated
when
CS = 1 or RST = 0. See Section 8.8.
RDY: Intel Mode (IFSEL = 100 or 110): RDY goes high when the read or write cycle can
progress.
ACK: Motorola Mode (IFSEL = 101 or 111): ACK goes low when the read or write cycle can
progress.
INT
Oz
Interrupt Output (Active Low, Open Drain, or Push-Pull). This pin is driven low in response
to one or more unmasked, active interrupt sources within the device.
INT remains low until the
interrupt is serviced or masked. When GLOBAL.CR2:INTM = 0,
INT is high impedance when
inactive (default). When INTM = 1,
INT is driven high when inactive. INT is high impedance
when
RST = 0. See Section 8.10.
GPIOAn
I/Opd
General-Purpose I/O A. When a microprocessor interface is enabled (IFSEL
≠ 000), this pin is
the “A” general-purpose I/O pin for port n. See Section 8.7.3.
GPIOBn
I/Opd
General-Purpose I/O B. When a microprocessor interface is enabled (IFSEL
≠ 000), this pin is
the “B” general-purpose I/O pin for port n. See Section 8.7.3. Note: GPIOB1, GPIOB2, and
GPIOB3 can also be programmed as global control/status pins.
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