參數(shù)資料
型號: DSM2150F5V
廠商: 意法半導(dǎo)體
元件分類: 數(shù)字信號處理
英文描述: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
中文描述: 帝斯曼(數(shù)字信號處理器系統(tǒng)內(nèi)存)的ADI公司的DSP(3.3V電源)
文件頁數(shù): 27/73頁
文件大?。?/td> 1067K
代理商: DSM2150F5V
27/73
DSM2150F5V
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See Applica-
tion Note
AN1171
for details on how to specify log-
ic using PSDsoft Express.
The CPLD has the following blocks:
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Product Term Allocator
AND Array capable of generating up to 190
product terms
Two I/O Ports.
I
I
I
I
I
Each of the blocks are described in the sections
that follow.
The IMCs and OMCs are connected to the device
internal data bus and can be directly accessed by
the DSP. This enables the DSP software to load
data into the OMC or read data from both the IMCs
and OMCs. This feature allows efficient implemen-
tation of system logic and eliminates the need to
connect the data bus to the AND Array as required
in most standard PLD macro cell architectures.
Figure 8. Macrocell and I/O Port
I/O PORTS
CPLD Macrocells
Input Macrocells
MUX
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
INPUT
Pfrom other
MacrocellS
POLARITY
PRUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT Output Enable (OE)
Macrocell Feedback
I/O Port Input
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
P
P
DSP ADDRESS / DATA BUS
MOut to
MCU
CDATA
A
CPLD OUTPUT
I/O Pin
AI05770
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參數(shù)描述
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DSM2150F5V-12T6T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM
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DSM2180F3_08 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply)
DSM2180F315K6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply)