參數(shù)資料
型號(hào): DSM2150F5V
廠商: 意法半導(dǎo)體
元件分類: 數(shù)字信號(hào)處理
英文描述: DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply)
中文描述: 帝斯曼(數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存)的ADI公司的DSP(3.3V電源)
文件頁數(shù): 56/73頁
文件大?。?/td> 1067K
代理商: DSM2150F5V
DSM2150F5V
56/73
Figure 27. Input to Output Disable / Enable
Table 22. CPLD Combinatorial Timing
Note: 1. Fast Slew Rate output available on Port C and Port F.
Symbol
Parameter
Conditions
-12
PT
Aloc
Turbo
Off
Slew
Rate
1
Unit
Min
Max
t
PD
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
43
Add 4
Add 20
Sub 6
ns
t
EA
CPLD Input to CPLD Output
Enable
45
Add 20
Sub 6
ns
t
ER
CPLD Input to CPLD Output
Disable
45
Add 20
Sub 6
ns
t
ARP
CPLD Register Clear or
Preset Delay
43
Add 20
Sub 6
ns
t
ARPW
CPLD Register Clear or
Preset Pulse Width
30
Add 20
ns
t
ARD
CPLD Array Delay
Any MicroCell
27
Add 4
ns
t
TURBO
Minimum time between
switching of any PLD inputs
which prevents PLD from
entering Standby Mode.
PLD inputs that
switch less
frequently than
this parameter
allow Standby
PLD Mode.
100
ns
tER
tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
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