- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376997 > DSM2150F5V (意法半導體) DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) PDF資料下載
參數(shù)資料
| 型號： | DSM2150F5V |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內存）的ADI公司的DSP（3.3V電源） |
| 文件頁數(shù)： | 71/73頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | DSM2150F5V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當前第71頁第72頁第73頁
71/73
DSM2150F5V
Table 48. Page Register
Note: Bit Definitions:
Configure Page input to PLD. Default is PGR7-PGR0=0.
Table 49. PMMR0 Register
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Note: Bit Definitions:
PLD Turbo
0 = PLD Turbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK
0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CLKIN to the PLD AND array is disconnected, saving power.
PLD MCells CLK
0 = CLKIN to the PLD Macrocells is connected.
1 = CLKIN to the PLD Macrocells is disconnected, saving power.
Table 50. PMMR2 Register
Note: For Bit 4, Bit 3, Bit 2: See Table
49
for the signals that are blocked on pins CNTL0-CNTL2.
Note: Bit Definitions:
PLD Array Addr
0 = Address A7-A0 are connected to the PLD array.
1 = Address A7-A0 are blocked from the PLD array, saving power.
PLD Array CNTL2
0 = CNTL2 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CNTL2 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL1
0 = CNTL1 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CNTL1 input to the PLD AND array is disconnected, saving power.
PLD Array CNTL0
0 = CNTL0 input to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo bit is off.
1 = CNTL0 input to the PLD AND array is disconnected, saving power.
PLD Array WRH
0 = WRH input to the PLD AND array is connected.
1 = WRH input to the PLD AND array is disconnected, saving power.
Table 51. Memory_ID0 Register
Note: Bit Definitions:
F_size[3:0]
6
h = Primary Flash memory size is 8Mbit
5h = Primary Flash memory size is 4Mbit
Table 52. Memory_ID1 Register
Note: Bit Definitions:
B_size[3:0]
3
h = Secondary NVM size is 512Kbit
2h = Secondary NVM size is 256Kbit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGR 7
PGR 6
PGR 5
PGR 4
PGR 3
PGR 2
PGR 1
PGR 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
PLD
MCells CLK
PLD
Array CLK
PLD
Turbo
not used
(set to 0)
not used
(set to 0)
not used
(set to 0)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
PLD
Array WRH
not used
(set to 0)
PLD Array
CNTL2
PLD Array
CNTL1
PLD Array
CNTL0
not used
(set to 0)
PLD
Array Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
not used
(set to 0)
not used
(set to 0)
F_size 3
F_size 2
F_size 1
F_size 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
not used
(set to 0)
not used
(set to 0)
not used
(set to 0)
not used
(set to 0)
B_size 3
B_size 2
B_size 1
B_size 0
相關PDF資料 |
PDF描述 |
|---|---|
| DSM2150F5V-12T6 | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| DSM2180F3 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| DSM2180F315K6 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| DSM2180F315T6 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
| DSM2180F390K6 | DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (5V Supply) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2150F5V-12T6 | 功能描述:SPLD - 簡單可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風格:Through Hole 封裝 / 箱體:DIP-24 |
| DSM2150F5V-12T6T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM |
| DSM2180F3 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply) |
| DSM2180F3_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) for analog devices ADSP-218X family (5 V supply) |
| DSM2180F315K6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DSM (Digital Signal Processor System Memory) For Analog Devices ADSP-218X Family (3.3V Supply) |
發(fā)布緊急采購，3分鐘左右您將得到回復。